ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 79
ATMEGA128RFA1-ZUR
Manufacturer Part Number
ATMEGA128RFA1-ZUR
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
Specifications of ATMEGA128RFA1-ZUR
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
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2467V–AVR–02/11
Table 37. Overriding Signals for Alternate Functions PD7..PD4
Table 38. Overriding Signals for Alternate Functions in PD3..PD0
Note:
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins
PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between
the AIO outputs shown in the port figure and the digital logic of the TWI module.
PD3/INT3/TXD1
TXEN1
0
TXEN1
1
TXEN1
TXD1
INT3 ENABLE
1
INT3 INPUT
–
PD7/T2
0
0
0
0
0
0
0
0
T2 INPUT
–
PD2/INT2/RXD1
RXEN1
PORTD2 • PUD
RXEN1
0
0
0
INT2 ENABLE
1
INT2 INPUT/RXD1
–
PD6/T1
0
0
0
0
0
0
0
0
T1 INPUT
–
PD5/XCK1
XCK1 INPUT
0
0
0
0
UMSEL1
XCK1 OUTPUT
0
0
–
PD1/INT1/SDA
TWEN
PORTD1 • PUD
TWEN
SDA_OUT
TWEN
0
INT1 ENABLE
1
INT1 INPUT
SDA INPUT
(1)
PD0/INT0/SCL
TWEN
PORTD0 • PUD
TWEN
SCL_OUT
TWEN
0
INT0 ENABLE
1
INT0 INPUT
SCL INPUT
PD4/ICP1
0
0
0
0
0
0
0
0
ICP1 INPUT
–
ATmega128
79
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