ATMEGA2560R231-CU Atmel, ATMEGA2560R231-CU Datasheet - Page 440

• Manufacturer Part Number: ATMEGA2560R231-CU
• Description: BUNDLE ATMEGA2560/RF231 PBGA
• Manufacturer: Atmel

Specifications of ATMEGA2560R231-CU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 256kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-CBGA and 32-QFN
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 8 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

2549M–AVR–09/10
23 2-wire Serial Interface .......................................................................... 241
24 AC – Analog Comparator .................................................................... 271
25 ADC – Analog to Digital Converter ..................................................... 275
26 JTAG Interface and On-chip Debug System ..................................... 296
27 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 302
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
24.1
24.2
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
27.1
27.2
Features ........................................................................................................241
2-wire Serial Interface Bus Definition ............................................................241
Data Transfer and Frame Format ..................................................................242
Multi-master Bus Systems, Arbitration and Synchronization .........................245
Overview of the TWI Module .........................................................................246
Using the TWI ................................................................................................249
Transmission Modes .....................................................................................252
Multi-master Systems and Arbitration ............................................................265
Register Description ......................................................................................266
Analog Comparator Multiplexed Input ...........................................................271
Register Description ......................................................................................272
Features ........................................................................................................275
Operation .......................................................................................................276
Starting a Conversion ....................................................................................277
Prescaling and Conversion Timing ................................................................278
Changing Channel or Reference Selection ...................................................282
ADC Noise Canceler .....................................................................................283
ADC Conversion Result .................................................................................288
Register Description ......................................................................................289
Features ........................................................................................................296
Overview ........................................................................................................296
TAP - Test Access Port .................................................................................297
Using the Boundary-scan Chain ....................................................................299
Using the On-chip Debug System .................................................................299
On-chip Debug Specific JTAG Instructions ...................................................300
Using the JTAG Programming Capabilities ...................................................301
Bibliography ...................................................................................................301
On-chip Debug Related Register in I/O Memory ...........................................301
Features ........................................................................................................302
System Overview ...........................................................................................302
ATmega640/1280/1281/2560/2561
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