TRC101 RFM, TRC101 Datasheet - Page 25

• Manufacturer Part Number: TRC101
• Description: RFIC TRANCEIVER MULTI-CHANNEL FS
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC101

• Frequency: 300MHz ~ 1GHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Applications: General Purpose
• Power - Output: 8dBm
• Sensitivity: -105dBm
• Voltage - Supply: 2.2 V ~ 5.4 V
• Current - Receiving: 17mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1093-2

FIFO Read Register
The FIFO Read Register stores the received data and can be read out by the host processor. The FIFO
must be enabled by setting Bit[6] of the Configuration Register.
Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the Data FIFO Configuration Register.
Bit [7..0] – FIFO Data Bits: These bits are the recovered data bits stored in the FIFO. These bits may be
read out over the SPI bus.
*Alternate Read Method
A faster method of reading the internal FIFO is recommended. The Rx FIFO is directly accessible by using
the nFSEL select pin (6) and monitoring the FINT interrupt pin (7) for pending data. Each data bit may be
clocked in on the rising edge of SCK.
Bit
15
1
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Bit
14
0
*NOTE: The internal FIFO cannot be accessed faster than f
Bit
13
1
Bit
12
1
nFSEL
nFINT
FIFO or data errors will occur. For a 10MHz ref xtal the max SCK <2.5MHz.
nCS
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SCK
SDO
Bit
11
0
[POR=B000h]
Figure 8. Recommended FIFO Read Method Timing
Bit
10
0
D 7
Bit
9
0
D 6
Bit
8
0
D 5
RX7
Bit
7
D 4
RX6
Bit
6
D 3
RX5
Bit
5
D 2
RX4
Bit
4
XTAL
/4 when reading the
D 1
RX3
Bit
3
D 0
RX2
Bit
2
TRC101 - 4/8/08
RX1
Bit
1
Page 25 of 42
RX0
Bit
0