XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 135

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RECEIVE TRANSPORT OVERHEAD INTERFACE
XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
P
W3
Y1
Y2
IN
#
RxLDCC
RxE1F1E2FP
RxE1F1E2
S
IGNAL
N
AME
I/O
O
O
O
S
CMOS Receive - Line DCC Output Port - Output Pin:
CMOS Receive - Order-Wire Output Port - Frame Boundary Indicator:
CMOS Receive - Order-Wire Output Port - Output Pin:
T
IGNAL
YPE
This output pin, along with RxLDCCVAL and the RxTOHClk output pins
function as the Receive Line DCC output port of the XRT94L43.
This pin outputs the contents of the Line DCC (e.g., the D4, D5, D6, D7,
D8, D9, D10, D11 and D12 bytes), within the incoming STS-12 data-
stream. The Receive Line DCC Output port will assert the RxLDCCVAL
output pin, in order to indicate that the data, residing on the RxLDCC out-
put pin is a valid Line DCC byte. The Receive Line DCC output port will
update the RxLDCCVAL and the RxLDCC output pins upon the falling
edge of the RxTOHClk output pin. The Line DCC HDLC circuitry that is
interfaced to this output pin, the RxLDCCVAL and the RxTOHClk pins is
suppose to do the following.
1. It should continuously sample and monitor the state of the RxLDCCVAL
output pin upon the rising edge of RxTOHClk.
2. Anytime the Line DCC HDLC circuitry samples the RxLDCCVAL output
pin "High", it should sample and latch the contents of this output pin (as a
valid Line DCC bit) into the Line DCC HDLC circuitry.
This output pin, along with RxE1F1E2, RxE1F1E2Val and the RxTOHClk
output pins function as the Receive Order-Wire Output port of the
XRT94L43.
This output pin pulses "High" (for one period of RxTOHClk) coincident to
when the very first bit (of the E1 byte) is being output via the RxE1F1E2
output pin.
This output pin, along with RxE1F1E2Val, RxE1F1F2FP, and the RxTO-
HClk output pins function as the Receive Order-Wire Output Port of the
XRT94L43.
This pin outputs the contents of the Order-Wire bytes (e.g., the E1, F1 and
E2 bytes) within the incoming STS-12 data-stream.
The Receive Order-Wire Output port will pulse the RxE1F1E2FP output
pin "High" (for one period of RxTOHClk) coincident to when the very first
bit (of the E1 byte) is being output via the RxE1F1E2 output pin. Addition-
ally, the Receive Order-Wire Output port will also assert the RxE1F1E2Val
output pin, in order to indicate that the data, residing on the RxE1F1E2
output pin is a valid Order-Wire byte.
The Receive Order-Wire output port will update the RxE1F1E2Val, the
RxE1F1E2FP and the RxE1F1E2 output pins upon the falling edge of the
RxTOHClk output pin.
The Receive Order-Wire circuitry that is interfaced to this output pin, and
the RxE1F1E2Val, the RxE1F1E2 and the RxTOHClk pins is suppose to
do the following;
1. It should continuously sample and monitor the state of the
RxE1F1E2Val and RxE1F1E2FP output pins upon the rising edge of
RxTOHClk.
2. Anytime the Order-wire circuitry samples the RxE1F1E2Val and
RxE1F1E2FP output pins "High", it should begin to sample and latch the
contents of this output pin (as a valid Order-Wire bit) into the Order-Wire
circuitry.
3. The Order-Wire circuitry should continue to sample and latch the con-
tents of the output pin until the RxE1F2E2Val output pin is sampled "Low".
129
D
ESCRIPTION
REV. 1.0.2