XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 6
XRT94L43IB-F
Manufacturer Part Number
XRT94L43IB-F
Description
IC MAPPER SONET/SDH OC12 516BGA
Manufacturer
Exar Corporation
Datasheet
1.XRT94L43IB.pdf
(328 pages)
Specifications of XRT94L43IB-F
Applications
Network Switches
Interface
Bus
Voltage - Supply
2.5V, 3.3V
Package / Case
516-BBGA
Mounting Type
Surface Mount
Product
Mapper
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L43IB-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XRT94L43IB-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
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REV. 1.0.2
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DS3 TRANSMIT FRAMER
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E3 RECEIVE FRAMER
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Provides 15-bit PRBS lock
Offers following frame generation mechanism: Asynchronous operation, using receive side clock, external
framing
Supports either C-bit operation or M13 operation: optional all C bits set to "1" or C-bit parity ID bit (C11)
toggled in each frame for M13 operation
Provides start of frame control with external pin
Inserts frame overhead bits via External serial port or Internal generation
Generates and checks parity
Automatically transmits the DS3 FERF/REI indicator whenever the DS3 Receiver declares either the DS3
LOS, DS3 AIS or DS3 OOF defect conditions.
Permits the user to control the DS3 FEBE/REI bit-fields via Software Control, or to automatically transmit the
FEBE/REI indicator whenever the DS3 Receiver detects CP-Bit or Framing (F or M) bit errors
Provides FEAC channel processing including generation of valid FEAC patterns and transmissions of all 1’s
upon programming of idle code
Inserts path maintenance data link through HDLC transmitter which contains the following features:
LOS Insertion enabled by register bit
AIS Insertion enabled by register bit or pin
Idle signal insertion enabled by register bit
Supports B3ZS encoding
Generates AIS, Idle and Yellow force alarms
Inserts errors optionally in the P, F, FEBE and M bits
Provides 15-bit PRBS generator
Offers off-line framing algorithm
Complies with standards as: ITU-T G.751 and G.832
Provides line code violation detection and excess zero count
LAPD controller complies with ITU Q.921 LAPD protocol
Provides local loop-back
Supports G.751 and G.832 framing formats
Supports HDB3 line decoding which can be user enabled. Replaces valid B00V or 000V with 4 zero’s
AM for storage of entire LAPD message
Selection of message length to 82 or 76 bytes
Optional frame header generation
Generation of flag sequences
Computation and insertion of CRC
Zero stuffing
Register bits for communication with microprocessor
Interrupt generation upon transmission of message
6
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
XRT94L43
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