XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 60

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
STS-3/STM-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION
P
A22
IN
#
STS3TxA_D_0_6
TxSBDATA_6
DS3/E3/
STS1_CLK_IN_4
S
IGNAL
N
AME
I/O
I
S
T
IGNAL
TTL
YPE
Transmit STS-3/STM-1 Telecom Bus - Channel 0 - Input Data Bus
Pin Number 6/DS3/E3 Framer or Receive STS-1 TOH Processor
block line interface clock input Pin - Channel 4:
The function of this pin depends upon whether or not the STS-3/
STM-1 Telecom Bus Interface, associated with Channel 0 is enabled.
If STS-3/STM-1 Telecom Bus (Channel 0) has been enabled -
STS-3/STM-1 Transmit Telecom Bus - Input Data Bus Pin Num-
ber 6: STS3TxA_D_0_6:
function as the STS-3/STM-1 Transmit (Add) Telecom Bus - Input
Data Bus for Channel 0. The STS-3/STM-1 Telecom Bus interface
will sample and latch this pin upon the falling edge of
STS3TxA_CLK_0.
If STS-3/STM-1 Telecom Bus (Channel 0) is disabled - DS3/E3/
STS1_CLK_IN - DS3/E3/STS-1 Line Interface Clock Input - Chan-
nel 4:
This input accepts a recovered DS3, E3 or STS-1 clock signal (from
a DS3/E3/STS-1 LIU IC). This input pin should be connected to the
RCLK output of the DS3/E3/STS-1 LIU IC (corresponding to channel
4).
The XRT94L43 uses this clock signal to sample and latch the data
that is applied to the DS3/E3/STS1_DATA_IN_4 input pin number
B23.
By default, the data that is applied to the DS3/E3/STS1_DATA_IN_4
input pin will be latched into the XRT94L43 upon the falling edge of
this clock signal.
For DS3/E3 Applications
The XRT94L43 can be configured to latch the DS3/E3/
STS1_DATA_IN_4 signal upon the rising edge of this clock signal by
setting Bit 1 (DS3/E3/STS1_CLK_IN Invert), within the I/O Control
Register - Channel 4 (Indirect Address = 0x5E, 0x01), (Direct
Address = 0x5F01) to a "1".
For STS-1 Applications
The XRT94L43 can not be configured to sample the DS3/E3/
STS1_DATA_IN_4 signal upon the rising edge of this clock signal.
This input pin along with STS3TxA_D_0_7 and STS3TxA_D_0[5:0]
54
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
D
ESCRIPTION
XRT94L43