XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 170

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SONET/SDH OVERHEAD INTERFACE - TRANSMIT DIRECTION
REV. 1.0.2
AD12
AD13
AC13
AE17
AB12
AE11
AE13
AF19
AB13
P
AF11
AD8
AD9
C10
D18
AE8
D13
C18
C13
AF4
D19
AE9
D14
C19
C14
AF5
B13
A16
B10
A15
B16
E10
D9
IN
#
TxPOH_0
TxPOH_1
TxPOH_2
TxPOH_3
TxPOH_4
TxPOH_5
TxPOH_6
TxPOH_7
TxPOH_8
TxPOH_9
TxPOH_10
TxPOH_11
TxPOH_12
TxPOH_13
TxPOH_14
TxPOH_15
TxPOHClk_0
TxPOHClk_1
TxPOHClk_2
TxPOHClk_3
TxPOHClk_4
TxPOHClk_5
TxPOHClk_6
TxPOHClk_7
TxPOHClk_8
TxPOHClk_9
TxPOHClk_10
TxPOHClk_11
TxPOHClk_12
TxPOHClk_13
TxPOHClk_14
TxPOHClk_15
S
IGNAL
N
AME
I/O
O
I
S
CMOS
T
IGNAL
TTL
YPE
If the user is inserting both POH and TOH data via these input pins:
(Continued)
The TxPOHFrame_n output pin will toggle "High" twice during a given
STS-1 frame period. First, this output pin will toggle "High" coincident
with the TxPOH port being ready to accept and process the A1 byte
(e.g., the very first TOH byte). Second, this output pin will toggle "High"
coincident with the TxPOH port being ready to accept and process the
J1 byte (e.g., the very first POH byte).
If the externally circuitry samples the TxPOHFrame_n output pin "High",
and the TxPOHEnable_n output pin "Low", then the TxPOH port is now
ready to accept and process the very first TOH byte.
If the externally circuitry samples the TxPOHFrame_n output pin "High"
and the TxPOHEnable_n output pin "High", then the TxPOH port is now
ready to accept and process the very first POH byte.
To externally insert a given POH or TOH byte, do the following;
(1) Assert the TxPOHIns_n input pin by toggling it "High" and,
(2) place the value of the first bit (within this particular POH or TOH byte)
on this input upon the very next falling edge of TxPOHClk_n.
This data bit will be sampled upon the very next rising edge of
TxPOHClk_n. The external circuitry should continue to keep the
TxPOHIns_n input pin "High" and advancing the next bits (within the
POH bytes) upon each falling edge of TxPOHClk_n.
N
Transmit Path Overhead Input Port - Clock Output pin:
These output pins, along with TxPOH_n, TxPOHEnable_n,
TxPOHIns_n and TxPOHFrame_n function as the Transmit Path Over-
head (TxPOH) Input Port.
The TxPOHFrame_n and TxPOHEnable_n output pins are updated
upon the falling edge this clock output signal. The TxPOHIns_n input
pins and the data residing on the TxPOH_n input pins are sampled on
the rising edge of this clock signal.
OTES
1. If POH data is externally inserted into each of the 12 Transmit
2. TOH data can be externally inserted into each of the 12
:
SONET POH Processor blocks, then these input pins cannot
be used to externally insert POH data into each of the 12
Transmit STS-1 POH Processor blocks.
Transmit STS-1 TOH Processor blocks, only if POH data is
NOT externally inserted into each of the 12 Transmit SONET
POH Processor blocks.
164
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
D
ESCRIPTION
XRT94L43