AT32UC3C164C-AUR Atmel, AT32UC3C164C-AUR Datasheet - Page 24

• Manufacturer Part Number: AT32UC3C164C-AUR
• Description: IC MCU AVR32 64K FLASH 100TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3C164C-AUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 81
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 3-7.
3.4
3.4.1
3.4.2
3.4.3
3.4.4
32117BS–AVR-03/11
Signal Name
DP
VBUS
ID
VBOF
I/O Line Considerations
JTAG pins
RESET_N pin
TWI pins
GPIO pins
Signal Description List
Function
USB Device Port Data +
USB VBUS Monitor and OTG Negociation
ID Pin of the USB Bus
USB VBUS On/off: bus power control port
The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI
pins have pull-up resistors when JTAG is enabled. The TCK pin always have pull-up enabled
during reset. The TDO pin is an output, driven at VDDIO1, and has no pull-up resistor. The
JTAG pins can be used as GPIO pins and muxed with peripherals when the JTAG is disabled.
Please refer to
The RESET_N pin integrates a pull-up resistor to VDDIO1. As the product integrates a power-on
reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to
be applied to the product.
The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debug-
ging, it must not be driven by external circuitry.
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the
pins have the same characteristics as GPIO pins.
All I/O lines integrate programmable pull-up and pull-down resistors. Most I/O lines integrate
drive strength control, see
drive strength is performed independently for each I/O line through the GPIO Controllers.
After reset, I/O lines default as inputs with pull-up/pull-down resistors disabled. After reset, out-
put drive strength is configured to the lowest value to reduce global EMI of the device.
When the I/O line is configured as analog function (ADC I/O, AC inputs, DAC I/O), the pull-up
and pull-down resistors are automatically disabled.
Section 3.2.4
Table
for the JTAG port connections.
3-1. Programming of this pull-up and pull-down resistor or this
Analog
Analog
output
Type
Input
Input
Active
Level
Comments
AT32UC3C
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