AT32UC3C164C-AUR Atmel, AT32UC3C164C-AUR Datasheet - Page 85

• Manufacturer Part Number: AT32UC3C164C-AUR
• Description: IC MCU AVR32 64K FLASH 100TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3C164C-AUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 81
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 7-56.
Note:
32117BS–AVR-03/11
Symbol
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
23
24
25
26
cess technology. These values are not covered by test limits in production.
SDRAM Signal
Parameter
SDCKE high before SDCK rising edge
SDCKE low after SDCK rising edge
SDCKE low before SDCK rising edge
SDCKE high after SDCK rising edge
SDCS low before SDCK rising edge
SDCS high after SDCK rising edge
RAS low before SDCK rising edge
RAS high after SDCK rising edge
SDA10 change before SDCK rising edge
SDA10 change after SDCK rising edge
Address change before SDCK rising edge
Address change after SDCK rising edge
Bank change before SDCK rising edge
Bank change after SDCK rising edge
CAS low before SDCK rising edge
CAS high after SDCK rising edge
DQM change before SDCK rising edge
DQM change after SDCK rising edge
D0-D15 in setup before SDCK rising edge
D0-D15 in hold after SDCK rising edge
SDWE low before SDCK rising edge
SDWE high after SDCK rising edge
D0-D15 Out valid before SDCK rising edge
D0-D15 Out valid after SDCK rising edge
(1)
drive strength of the pads set to
external capacitor = 40pF on
except 8 pF on SDCK pins
SDRAM pins
V
Conditions
the highest,
VDD
= 3.0V,
Min
AT32UC3C
8.4
6.4
5.6
5.6
7.3
6.8
8.3
6.1
7.7
7.1
4.7
4.4
6.2
6.9
6.6
7.8
6.7
6.4
7.4
5.2
7
6
0
7
Units
ns
85