AT32UC3C164C-AUR Atmel, AT32UC3C164C-AUR Datasheet - Page 34

• Manufacturer Part Number: AT32UC3C164C-AUR
• Description: IC MCU AVR32 64K FLASH 100TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3C164C-AUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 81
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.5
32117BS–AVR-03/11
Exceptions and Interrupts
Table 4-3.
In the AVR32 architecture, events are used as a common term for exceptions and interrupts.
AVR32UC incorporates a powerful event handling scheme. The different event sources, like Ille-
gal Op-code and interrupt requests, have different priority levels, ensuring a well-defined
behavior when multiple events are received simultaneously. Additionally, pending events of a
higher priority class may preempt handling of ongoing events of a lower priority class.
When an event occurs, the execution of the instruction stream is halted, and execution is passed
to an event handler at an address specified in
placed sequentially in the code space starting at the address specified by EVBA, with four bytes
between each handler. This gives ample space for a jump instruction to be placed there, jump-
ing to the event routine itself. A few critical handlers have larger spacing between them, allowing
the entire event routine to be placed directly at the address specified by the EVBA-relative offset
generated by hardware. All interrupt sources have autovectored interrupt service routine (ISR)
addresses. This allows the interrupt controller to directly specify the ISR address as an address
Reg #
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112-191
192-255
Address
360
364
368
372
376
380
384
388
392
396
400
404
408
412
416
420
424
428
432
436
440
444
448-764
768-1020
System Registers (Continued)
Name
MPUPSR2
MPUPSR3
MPUPSR4
MPUPSR5
MPUPSR6
MPUPSR7
MPUCRA
MPUCRB
MPUBRA
MPUBRB
MPUAPRA
MPUAPRB
MPUCR
SS_STATUS
SS_ADRF
SS_ADRR
SS_ADR0
SS_ADR1
SS_SP_SYS
SS_SP_APP
SS_RAR
SS_RSR
Reserved
IMPL
Function
MPU Privilege Select Register region 2
MPU Privilege Select Register region 3
MPU Privilege Select Register region 4
MPU Privilege Select Register region 5
MPU Privilege Select Register region 6
MPU Privilege Select Register region 7
Unused in this version of AVR32UC
Unused in this version of AVR32UC
Unused in this version of AVR32UC
Unused in this version of AVR32UC
MPU Access Permission Register A
MPU Access Permission Register B
MPU Control Register
Secure State Status Register
Secure State Address Flash Register
Secure State Address RAM Register
Secure State Address 0 Register
Secure State Address 1 Register
Secure State Stack Pointer System Register
Secure State Stack Pointer Application Register
Secure State Return Address Register
Secure State Return Status Register
Reserved for future use
IMPLEMENTATION DEFINED
Table 4-4 on page
38. Most of the handlers are
AT32UC3C
34