S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 205

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The trigger priorities described in
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
6.3.2.7.2
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state whilst in State2. The matches refer to the match channels of the comparator match
control logic as depicted in
by setting the comparator enable bit in the associated DBGXCTL control register.
Freescale Semiconductor
Address: 0x0027
SC[3:0]
SC[3:0]
0000
0001
0010
0011
0100
Reset
Field
3–0
SC[3:0]
W
R
0111
1000
1001
1010
1011
1100
1101
1110
1111
These bits select the targeted next state whilst in State2, based upon the match event.
0
0
7
Debug State Control Register 2 (DBGSCR2)
= Unimplemented or Reserved
Table 6-20. State1 Sequencer Next State Selection (continued)
Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
Figure 6-10. Debug State Control Register 2 (DBGSCR2)
0
0
6
Table 6-22. State2 —Sequencer Next State Selection
Figure 6-1
Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2
Table 6-21. DBGSCR2 Field Descriptions
Match3 triggers to State1....... Other matches have no effect
Match3 triggers to State3....... Other matches have no effect
S12XS Family Reference Manual, Rev. 1.11
Table 6-39
0
0
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
5
and described in
Any match triggers to Final State
dictate that in the case of simultaneous matches, the match
Any match triggers to state1
Any match triggers to state3
0
0
4
Description
Description
Section
Description
SC3
0
3
6.3.2.8.1”. Comparators must be enabled
SC2
0
2
S12X Debug (S12XDBGV3) Module
SC1
0
1
SC0
0
0
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