S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 553

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.4.3
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an ECC fault.
18.4.3.1
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with
the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed
description of the register bits involved, refer to
(FCNFG)”,
Status Register
The logic used for generating the Flash module interrupts is shown in
Freescale Semiconductor
Register
FSTAT
Flash Command Complete
ECC Double Bit Fault on Flash Read
ECC Single Bit Fault on Flash Read
Section 18.3.2.6, “Flash Error Configuration Register
Interrupts
Description of Flash Interrupt Operation
Vector addresses and their relative interrupt priority are determined at the
MCU level.
(FSTAT)”, and
Interrupt Source
MGSTAT1
MGSTAT0
ACCERR
Error Bit
Table 18-64. Erase D-Flash Sector Command Error Handling
FPVIOL
Section 18.3.2.8, “Flash Error Status Register
S12XS Family Reference Manual, Rev. 1.11
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see
Set if an invalid global address [22:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
Set if the selected area of the D-Flash memory is protected
Set if any errors have been encountered during the verify operation
Set if any non-correctable errors have been encountered during the verify
operation
Table 18-65. Flash Interrupt Sources
(FERSTAT register)
(FERSTAT register)
(FSTAT register)
Interrupt Flag
DFDIF
SFDIF
Section 18.3.2.5, “Flash Configuration Register
CCIF
NOTE
Error Condition
(FERCNFG register)
(FERCNFG register)
(FCNFG register)
(FERCNFG)”,
Local Enable
256 KByte Flash Module (S12XFTMR256K1V1)
DFDIE
SFDIE
CCIE
Figure
Table
18-27.
(FERSTAT)”.
Section 18.3.2.7, “Flash
18-28)
Global (CCR)
Mask
I Bit
I Bit
I Bit
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