WJLXT972MLC.A4-864115 Cortina Systems Inc, WJLXT972MLC.A4-864115 Datasheet
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Cortina Systems 10/100 Mbps PHY Transceiver Datasheet ® The Cortina Systems LXT972M Single-Port 10/100 Mbps PHY Transceiver (LXT972M PHY) directly supports both 100BASE-TX and 10BASE-T applications. The LXT972M PHY is IEEE compliant and provides a Media Independent Interface (MII) for ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA SYSTEMS NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Contents 1.0 Introduction to This Document .................................................................................................. 10 1.1 Document Overview ...........................................................................................................10 1.2 Related Documents ............................................................................................................ 10 2.0 Block Diagram ............................................................................................................................. 11 3.0 Ball and Pin Assignments .......................................................................................................... 12 4.0 Signal ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.8.8 10BASE-T Polarity Correction ............................................................................... 43 5.9 Monitoring Operations ........................................................................................................ 43 5.9.1 Monitoring Auto-Negotiation .................................................................................. 43 5.9.2 Monitoring Next Page Exchange ........................................................................... 44 5.9.3 LED Functions ....................................................................................................... 44 5.9.4 LED Pulse ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figures 1 Block Diagram ............................................................................................................................... 11 2 48-Pin LQFP Package: Pin Assignments ...................................................................................... 13 3 Management Interface Read Frame Structure ............................................................................. 24 4 Management Interface Write Frame Structure ............................................................................. 24 5 ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Tables 1 Related Documents ....................................................................................................................... 10 2 PHY Signal Types ......................................................................................................................... 12 3 LQFP Numeric Pin List .................................................................................................................. 13 4 PHY Signal Types ......................................................................................................................... 16 5 LXT972M: MII Data Interface Signal ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 49 Register Set for Product-Specific Registers ..................................................................................72 50 Configuration Register - Address 16, Hex 10 ................................................................................ 72 51 Status Register #2 - Address 17, Hex 11 ...................................................................................... 73 52 Interrupt Enable ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Revision History • Removed outdated Figure 3: 64-Pin Pb-Free LQFP Package: Pins Assignments • Removed the ordering information. This information is now available from www.cortina-systems.com. Added Section 10.0, Package Specifications First ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Section 5.2.1.1, Twisted-Pair Interface - Added text on MDI crossover. Section 5.2.1.5, Comment: for LXT972A/972M/977-->Remote Fault Detection and Reporting Section 5.3.2.1, External Crystal/Oscillator Table 37, Hardware Configuration Settings for Cortina Systems® ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 1.0 Introduction to This Document This document includes information on the Cortina Systems 100 Mbps PHY Transceiver (LXT972M PHY). 1.1 Document Overview This document includes the following subjects: 2.0, Block Diagram, ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 2.0 Block Diagram Figure 1 Block Diagram RESET_L Management / ADDR[1:0] Mode Select MDIO Register Set Logic MDC TX_EN TXD[3:0] Parallel/Serial Converter TX_CLK Register Set LED/CFG[3:1] Collision COL Detect RX_CLK RXD[3:0] ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 3.0 Ball and Pin Assignments See the following diagrams for signal placement: • Figure 2, 48-Pin LQFP Package: Pin Assignments, on page 13 See the following tables for signal lists: • ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 2 48-Pin LQFP Package: Pin Assignments VCCD 39 RX_CLK 40 RX_ER 41 TX_CLK 42 TX_EN 43 TXD0 44 TXD1 45 TXD2 46 TXD3 47 COL 48 ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 3 LQFP Numeric Pin List (Sheet Pin Symbol 9 GND 10 ADDR0 11 ADDR1 12 RBIAS 13 GNDA 14 TPOP 15 TPON 16 VCCA 17 TPIP 18 ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 3 LQFP Numeric Pin List (Sheet Pin Symbol 46 TXD2 47 TXD3 48 COL ® Cortina Systems LXT972M Single-Port 10/100 Mbps PHY Transceiver 3.0 Ball and Pin ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 4.0 Signal Descriptions Cortina recommends the following configurations for unused pins: • Unused inputs. Configure all unused inputs and unused multi-function pins for inactive states. • Unused outputs. Leave all unused ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 5 LXT972M: MII Data Interface Signal Descriptions LQFP Symbol Pin# 47 TXD3 46 TXD2 45 TXD1 44 TXD0 43 TX_EN 42 TX_CLK 33 RXD3 34 RXD2 35 RXD1 36 RXD0 ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 6 LXT972M: MII Controller Interface Signal Descriptions LQFP Symbol Pin# 32 MDC 31 MDIO Table 7 LXT972M: Network Interface Signal Descriptions LQFP Symbol Pin# 14 TPOP 15 TPON 17 TPIP ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 9 LXT972M: Configuration and LED Driver Signal Descriptions (Sheet LQFP Symbol Pin# 12 RBIAS 2 REFCLK/ LED/CFG3 27 LED/CFG2 28 LEDCFG1 Table 10 LXT972M: ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 11 LXT972M: JTAG Test Signal Descriptions (Sheet LQFP Symbol Pin# 21 TMS 22 TCK 23 TRST_L Table 12 LXT972M:Pin Types and Modes Modes RXD3:0 HWReset DL SFTPWRDN ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.0 Functional Description This chapter has the following sections: • Section 5.1, Device Overview, on page 21 • Section 5.2, Network Media / Protocol Support, on page 22 • Section 5.3, ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 The OSP signal processing scheme also requires substantially less computational logic than traditional DSP-based designs. This lowers power consumption and also reduces the logic switching noise generated by DSP engines. This ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 characteristics. On the receive side, the internal impedance is high enough that it has no practical effect on the external termination circuit. (For the slew rate settings, see Table 56, Transmit ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 The LXT972M PHY supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.2.3.2 Hardware Control Interface The LXT972M PHY provides a Hardware Control Interface for applications where the MDIO is not desired. The Hardware Control Interface uses the hardware configuration pins to set ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 • Section 5.4.2, Reduced-Power Modes • Section 5.4.3, Reset • Section 5.4.4, Hardware Configuration Settings When the LXT972M PHY is first powered on, reset, or encounters a link failure state, it ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.4.1 MDIO Control Mode and Hardware Control Mode In the MDIO Control mode, the LXT972M PHY reads the Hardware Control Interface pins to set the initial (default) values of the MDIO ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 during the last hardware reset. Therefore, any changes to pin values made since the last hardware reset are not detected during a software reset. • During a software reset, registers are ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.5.1 Auto-Negotiation Figure 6 Link Establishment Overview Disable Auto-Negotiation Go To Forced Settings Done If not configured for forced operation, the LXT972M PHY attempts to auto-negotiate with its link partner by ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 for software. This register bit is cleared when a new negotiation occurs, preventing the user from reading an old value in Register 6 and assuming there is valid information in Registers ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 • RX_DV • RX_ER • RXD[3:0] The following signals are used to transmit data from the MAC: • TX_CLK • TX_EN • TXD[3:0] The LXT972M PHY supplies both clock signals as ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 8 Clocking for 100BASE-X TX_CLK RX_CLK XI Figure 9 Clocking for Link Down Clock Transition RX_CLK TX_CLK 5.6.2 Transmit Enable The MAC must assert TX_EN the same time as the ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.6.4 Carrier Sense Carrier Sense (CRS asynchronous output. • CRS is always generated when the LXT972M PHY receives a packet from the line. • CRS is also generated when ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 10 Loopback Paths LXT97x PHY Operational Loopback 10T MII Loopback 5.6.7.1 Operational Loopback • Operational loopback is provided for 10 Mbps half-duplex links when register bit 16 Data ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.7 100 Mbps Operation 5.7.1 100BASE-X Network Operations During 100BASE-X operation, the LXT972M PHY transmits and receives 5-bit symbols across the network link. Figure 11 shows the structure of a standard ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 12 100BASE-TX Data Path Standard Data Flow D0 Parallel to Serial Serial to D3 Parallel Scrambler Bypass Data Flow S0 Parallel to S1 Serial ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 14 100BASE-TX Reception with Invalid Symbol RX_CLK RX_DV RXD<3:0> preamble SFD SFD DA RX_ER 5.7.2 Collision Indication Figure 15 shows normal transmission. Figure 15 100BASE-TX Transmission with No Errors TX_CLK ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.7.3 100BASE-X Protocol Sublayer Operations With respect to the 7-layer communications model, the LXT972M PHY is a Physical Layer 1 (PHY) device. The LXT972M PHY implements the following sublayers of the ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 16 4B/5B Coding (Sheet Code Code Type ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 16 4B/5B Coding (Sheet Code Code Type Undefined Undefined Undefined Undefined Undefined INVALID Undefined Undefined Undefined Undefined Undefined Undefined 1. The /I/ ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.7.3.2.3 Carrier Sense For 100BASE-TX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes assertion of carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes de-assertion of ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.7.3.3.4 Programmable Slew Rate Control The LXT972M PHY device supports a programmable slew-rate mechanism whereby one of four pre-selected slew rates can be used. (For details, see Register - Address 30, ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 • If the Link Integrity Test function is disabled (which can be done by setting Configuration register bit 16.14 to ‘1’), the LXT972M PHY transmits to the connection regardless of detected ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.9.2 Monitoring Next Page Exchange The LXT972M PHY offers an Alternate Next Page mode to simplify the next page exchange process. Normally, register bit 6.1 (Page Received) remains set until read. ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 When an event such as receiving a packet occurs, the event is edge detected and it starts the stretch timer. The LED driver remains asserted until the stretch timer expires. If ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 5.10.4 Boundary Scan Register Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the serial shift stage and the parallel output stage. operation. ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 6.0 Application Information 6.1 Magnetics Information The LXT972M PHY requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 19 Typical Twisted-Pair Interface - Switch LXT97x PHY 1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 20 Typical Twisted-Pair Interface - NIC LXT97x PHY SD/TP_L 1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 21 show a typical media independent interface (MII) for the LXT972M PHY. Figure 21 Typical Media Independent Interface MAC ® Cortina Systems LXT972M Single-Port 10/100 Mbps PHY Transceiver TX_EN TX_ER ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 7.0 Electrical Specifications This chapter includes test specifications for the LXT972M PHY. These specifications are guaranteed by test except where noted “by design”. Caution: Exceeding the absolute maximum rating values may ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 22 Recommended Operating Conditions (Sheet Parameter Hard Power Down Soft Power Down Auto-Negotiation 1. Typical values are at 25 °C and are for design aid only, not ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 25 I/O Characteristics - REFCLK/XI and XO Pins Parameter Input Low Voltage Input High Voltage Input Clock Frequency Tolerance 2 Input Clock Duty Cycle Input Capacitance 1. Typical values are ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 28 10BASE-T PHY Characteristics Parameter Peak differential output voltage Transition timing jitter added by the MAU and PLS sections Receive Input Impedance Differential Squelch Threshold Table 29 10BASE-T Link Integrity ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 • Figure 26, 10BASE-T Jabber and Unjabber Timing, on page 59 • Figure 27, 10BASE-T SQE (Heartbeat) Timing, on page 59 • Figure 28, Auto-Negotiation and Fast Link Pulse Timing, on ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 31 100BASE-TX Receive Timing Parameters - 4B Mode Parameter RXD[3:0], RX_DV, RX_ER RX_CLK High RXD[3:0], RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD[3:0], RX_DV Receive start of “J” ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 24 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS TPI COL Table 32 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 25 10BASE-T Transmit Timing TX_CLK t TXD, TX_EN, TX_ER CRS TPO ® Cortina Systems LXT972M Single-Port 10/100 Mbps PHY Transceiver 7.2 AC Timing ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 26 10BASE-T Jabber and Unjabber Timing TX_EN TXD COL Table 33 10BASE-T Jabber and Unjabber Timing Parameter Maximum transmit time Unjabber time 1. Typical values are at 25 °C and ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 28 Auto-Negotiation and Fast Link Pulse Timing TPOP Figure 29 Fast Link Pulse Timing TPOP Table 35 Auto-Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 30 MDIO Input Timing MDC MDIO Figure 31 MDIO Output Timing MDC MDIO Table 36 MDIO Timing Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Figure 32 Power-Up Timing VCC MDIO, and so on Table 37 Power-Up Timing Parameter Voltage threshold 2 Power Up delay 1. Typical values are at 25° C and are for design ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 38 RESET_L Pulse Width and Recovery Timing Parameter RESET_L pulse width RESET_L recovery delay2 1. Typical values are at 25° C and are for design aid only, not guaranteed, and ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 8.0 Register Definitions - IEEE Base Registers This chapter includes definitions for the IEEE base registers used by the LXT972M PHY. Section 9.0, Register Definitions - Product-Specific Registers additional product-specific LXT972M ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 40 Control Register - Address 0, Hex 0 Bit Name 0.15 Reset 0.14 Loopback 0.13 Speed Selection Auto-Negotiation 0.12 Enable 0.11 Power-Down 0.10 Isolate Restart Auto- 0.9 Negotiation 0.8 Duplex ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 41 MII Status Register #1 - Address 1, Hex 1 Bit Name 100BASE-T4 1.15 Not Supported 100BASE-X Full- 1.14 Duplex 100BASE-X Half- 1.13 Duplex 1.12 10 Mbps Full-Duplex 1.11 10 ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 42 PHY Identification Register 1 - Address 2, Hex 2 Bit Name Note: See Figure 34 for identifier bit mapping. 2.15:0 PHY ID Number Read Only Table ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 44 Auto-Negotiation Advertisement Register - Address 4, Hex 4 Bit Name 4.15 Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved 4.11 Asymmetric Pause 4.10 Pause 4.9 100BASE-T4 100BASE-TX full-duplex ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 45 Auto-Negotiation Link Partner Base Page Ability Register - Address 5, Hex 5 Bit Name 5.15 Next Page 5.14 Acknowledge 5.13 Remote Fault 5.12 Reserved 5.11 Asymmetric Pause 5.10 Pause ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 46 Auto-Negotiation Expansion - Address 6, Hex 6 Bit Name 6.15:6 Reserved 6.5 Base Page Parallel 6.4 Detection Fault Link Partner Next 6.3 Page Able 6.2 Next Page Able 6.1 ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 48 Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 Bit Name 8.15 Next Page (NP) 8.14 Acknowledge (ACK) 8.13 Message Page (MP) Acknowledge 2 8.12 (ACK2) ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 9.0 Register Definitions - Product-Specific Registers This chapter includes definitions of product-specific LXT972M PHY registers that are defined in accordance with the IEEE 802.3 standard for adding unique device functions. (For ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 50 Configuration Register - Address 16, Hex 10 (Sheet Bit Name TP Loopback 16.8 (10BASE-T) CRS Select 16.7 (10BASE-T) 16.6 Reserved 16.5 PRE_EN 16.4:3 Reserved 16.2 Reserved ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 51 Status Register #2 - Address 17, Hex 11 (Sheet Bit Name Auto-Negotiation 17.7 Complete 17.6 Reserved 17.5 Polarity 17.4 Pause 17:3 Error 17:2 Reserved 17:1 Reserved ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 52 Interrupt Enable Register - Address 18, Hex 12 Bit Name 18. Reserved 15:9 18.8 Reserved 18.7 ANMSK 18.6 SPEEDMSK 18.5 DUPLEXMSK 18.4 LINKMSK 18.3 Reserved 18.2 Reserved 18.1 Reserved ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 53 Status Change Register - Address 19, Hex 13 (Sheet Bit Name 19.4 LINKCHG 19.3 Reserved 19.2 Reserved 19.1 Reserved 19.0 Reserved 1. R/W = Read/Write, RO ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 54 LED Configuration Register - Address 20, Hex 14 (Sheet Bit Name LED1 20.15:12 Programming bits LED2 20.11:8 Programming bits 1. R/W = Read /Write ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 54 LED Configuration Register - Address 20, Hex 14 (Sheet Bit Name LED3 20.7:4 Programming bits 5 20.3:2 LEDFREQ PULSE- 20.1 STRETCH 20.0 Reserved 1. R/W = ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 Table 55 Digital Configuration Register - Address 26, Hex 1A (Sheet Bit Name 26.5:4 Reserved 26.3 Reserved 26.2:0 Reserved 1. R/W = Read /Write Read Only ...
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LXT972M PHY Datasheet 302875, Revision 5.2 13 September 2007 10.0 Package Specifications Figure 35 LQFP Package Specifications 48-Pin Low-Profile Quad Flat Pack Note: The package figure is generic and used only to demonstrate package dimensions. C0.55 (in MM ...
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For additional product and ordering information: www.cortina-systems.com ~ End of Document ~ TM ...