WJLXT972MLC.A4-864115 Cortina Systems Inc, WJLXT972MLC.A4-864115 Datasheet - Page 63

• Manufacturer Part Number: WJLXT972MLC.A4-864115
• Description: TXRX ETH 10/100 SGL PORT 48-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT972MLC.A4-864115

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1044

LXT972M PHY
Datasheet
302875, Revision 5.2
13 September 2007
Table 38
Cortina Systems
RESET_L Pulse Width and Recovery Timing
®
RESET_L pulse width
RESET_L recovery
1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
LXT972M Single-Port 10/100 Mbps PHY Transceiver
testing.
performance. The PHY comes out of reset after a delay of no more than 300 μ s. System designers should
consider this value as a minimum value. After de-asserting RESET_L, the MAC should delay no less than
300 μ s before accessing the MDIO port.
Parameter
delay2
Symbol
t1
t2
Min
10
–
Typ
–
1
Max
300
–
Units
7.2 AC Timing Diagrams and
ns
μ s
Test Conditions
–
–
Parameters
Page 63