WJLXT972MLC.A4-864115 Cortina Systems Inc, WJLXT972MLC.A4-864115 Datasheet - Page 45

• Manufacturer Part Number: WJLXT972MLC.A4-864115
• Description: TXRX ETH 10/100 SGL PORT 48-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT972MLC.A4-864115

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1044

LXT972M PHY
Datasheet
302875, Revision 5.2
13 September 2007
Figure 18
5.10
Note:
5.10.1
5.10.2
5.10.3
Cortina Systems
When an event such as receiving a packet occurs, the event is edge detected and it starts
the stretch timer. The LED driver remains asserted until the stretch timer expires. If
another event occurs before the stretch timer expires, then the stretch timer is reset and
the stretch time is extended.
When a long event (such as duplex status) occurs, the event is edge detected and it starts
the stretch timer. When the stretch timer expires, the edge detector is reset so that a long
event causes another pulse to be generated from the edge detector, which resets the
stretch timer and causes the LED driver to remain asserted.
Figure 18
LED Pulse Stretching
Boundary Scan (JTAG 1149.1) Functions
The LXT972M PHY includes a IEEE 1149.1 boundary scan test port for board level
testing. All digital input, output, and input/output pins are accessible.
For the related BSDL file, contact your local sales office or access the Cortina website
(www.cortina-systems.com).
Boundary Scan Interface
The boundary scan interface consists of five pins (TMS, TDI, TDO, TRST_L, and TCK). It
includes a state machine, data register array, and instruction register. The TMS and TDI
pins are pulled up internally. TCK is pulled down internally. TDO does not have an internal
pull-up or pull-down.
State Machine
The TAP controller is a state machine, with 16 states driven by the TCK and TMS pins.
Upon reset, the TEST_LOGIC_RESET state is entered. The state machine is also reset
when TMS and TDI are high for five TCK periods.
Instruction Register
After the state machine resets, the IDCODE instruction is always invoked. The decode
logic ensures the correct data flow to the Data registers according to the current
instruction.
Table 17
®
Event
LXT972M Single-Port 10/100 Mbps PHY Transceiver
LED
Note: The direct drive LED outputs in this diagram are shown as active Low.
lists valid LXT972M PHY JTAG instructions.
shows how the stretch operation functions.
stretch
stretch
stretch
5.10 Boundary Scan (JTAG
1149.1) Functions
B3475-01
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