ELLXT971ABE.A4-870479 Cortina Systems Inc, ELLXT971ABE.A4-870479 Datasheet
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Cortina Systems 10/100 Mbps PHY Transceiver Datasheet ® The Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver (LXT971A PHY) directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA SYSTEMS NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Contents 1.0 Introduction to This Document .................................................................................................. 10 1.1 Document Overview ...........................................................................................................10 1.2 Related Documents ............................................................................................................ 10 2.0 Block Diagram ............................................................................................................................. 11 3.0 Ball and Pin Assignments .......................................................................................................... 12 4.0 Signal ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.8.8 10BASE-T Polarity Correction ............................................................................... 50 5.9 Monitoring Operations ........................................................................................................ 50 5.9.1 Monitoring Auto-Negotiation .................................................................................. 50 5.9.2 Monitoring Next Page Exchange ........................................................................... 51 5.9.3 LED Functions ....................................................................................................... 51 5.9.4 LED Pulse ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figures 1 Block Diagram ............................................................................................................................... 11 2 64-Ball PBGA: Ball Assignments .................................................................................................. 13 3 64-Pin LQFP Package: Pins Assignments ................................................................................... 14 4 Management Interface Read Frame Structure ............................................................................. 28 5 Management ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Tables 1 Related Documents ....................................................................................................................... 10 2 PHY Signal Types ......................................................................................................................... 12 3 LQFP Numeric Pin List .................................................................................................................. 14 4 PHY Signal Types ......................................................................................................................... 17 5 MII Data Interface Signal Descriptions ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 49 PHY Identification Register 2 - Address 3, Hex 3 .......................................................................... 81 50 Auto-Negotiation Advertisement Register - Address 4, Hex 4....................................................... 82 51 Auto-Negotiation Link Partner Base Page Ability Register - ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Revision History • Removed outdated Figure 4: 64-Pin Pb-Free LQFP Package: Pins Assignments • Removed the ordering information. This information is now available from www.cortina-systems.com. Added Section 10.0, Package Specifications First ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Modified SD/TP description in Table 3 “LXT971A Network Interface Signal Added Table note 2. Modified Table 4 “LXT971A Miscellaneous Signal Modified Table 5 “LXT971A Power Supply Signal Added Table 8 “LXT971A ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 1.0 Introduction to This Document This document includes information on the Cortina Systems 100 Mbps PHY Transceiver (LXT971A PHY). 1.1 Document Overview This document includes the following subjects: 2.0, Block Diagram, ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 2.0 Block Diagram Figure 1 Block Diagram RESET_L Management / ADDR[4:0] Mode Select MDIO Register Set Logic MDC MDINT_L MDDIS TX_EN TXD[3:0] Parallel /Serial TX_ER Converter TX_CLK Register LED/CFG[3:1] Set Collision ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 3.0 Ball and Pin Assignments See the following diagrams for signal placement: • Figure 2, 64-Ball PBGA: Ball Assignments, on page 13 • Figure 3, 64-Pin LQFP Package: Pins Assignments, on ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 2 64-Ball PBGA: Ball Assignments 1 MDINT A CRS _L REF B COL CLK/XI RESET SLEW0 SLEW1 E ADDR0 ADDR1 F ADDR3 ADDR2 SD/ ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 3 64-Pin LQFP Package: Pins Assignments REFCLK/XI XO MDDIS RESET_L TXSLEW0 TXSLEW1 GND VCCIO NC NC GND ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 Table 3 LQFP Numeric Pin List (Sheet 1 ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 3 LQFP Numeric Pin List (Sheet Pin Symbol 16 ADDR4 17 RBIAS 18 GND 19 TPFOP 20 TPFON 21 VCCA 22 VCCA 23 TPFIP 24 TPFIN 25 ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 3 LQFP Numeric Pin List (Sheet Pin Symbol 54 TX_ER 55 TX_CLK 56 TX_EN 57 TXD0 58 TXD1 59 TXD2 60 TXD3 61 GND 62 COL 63 ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 4.0 Signal Descriptions Cortina recommends the following configurations for unused pins: • Unused inputs. Configure all unused inputs and unused multi-function pins for inactive states. • Unused outputs. Leave all unused ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 5 MII Data Interface Signal Descriptions PBGA LQFP Symbol Pin# Pin TXD3 B3 59 TXD2 C4 58 TXD1 A4 57 TXD0 B4 56 TX_EN C5 55 TX_CLK D6 ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 6 MII Controller Interface Signal Descriptions PBGA LQFP Symbol Pin# Pin MDDIS E7 43 MDC D8 42 MDIO A1 64 MDINT_L ® Cortina Systems LXT971A Single-Port 10/100 Mbps ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 7 Network Interface Signal Descriptions PBGA LQFP Symbol Pin# Pin TPFOP H3 20 TPFON H4 23 TPFIP H5 24 TPFIN G2 26 SD/TP_L Table 8 Standard Bus and ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 9 Configuration and LED Driver Signal Descriptions (Sheet PBGA LQFP Pin# Pin ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 10 Power, Ground, No-Connect Signal Descriptions PBGA LQFP Pin# Pin D4, E3, 7, 11, E4, F3, 18, 25, F4, C6, 34, 35, C3, G7, 41, 50 ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 12 Pin Types and Modes Modes RXD3:0 RX_DV HWReset DL SFTPWRDN DL HWPWRDN HZ HZ with HZ with ISOLATE ID SLEEP DL • Driven High (Logic 1) • ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.0 Functional Description This chapter has the following sections: • Section 5.1, Device Overview, on page 24 • Section 5.2, Network Media / Protocol Support, on page 25 • Section 5.3, ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 calculation truncation errors found in traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results in improved receiver noise and cross-talk performance. The OSP signal processing scheme also requires ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Only a transformer, RJ-45 connector, load resistor and bypass capacitors are required to complete this interface. On the transmit side, the LXT971A PHY has an active internal termination and does not ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 • When register bit 16 the LXT971A PHY does not transmit far end fault code. It continues to transmit idle code and may or may not drop link depending ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 The LXT971A PHY supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 • Register 18 provides interrupt enable and mask functions. Setting register bit 18 enables the device to request interrupt via the MDINT_L pin. An active Low on this pin ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 • VCCIO The digital and analog circuits require 3.3 V supplies (VCCA and VCCD). These inputs may be supplied from a single source. Each supply input must be de-coupled to ground. ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 7 Initialization Sequence MDIO Control MDIO Controlled Operation (MDIO Writes Enabled) Reset MDIO Registers to values read at H/W Control Interface at last Hardware Reset 5.4.1 MDIO Control Mode and ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 — 10BASE-T, Half-Duplex • Allow auto-negotiation/parallel-detection In the Hardware Control Mode, the LXT971A PHY disables direct-write operations to the MDIO registers through the MDIO Interface. On power-up or hardware reset, the ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.4.3 Reset The LXT971A PHY provides both hardware and software resets, each of which manage differently the configuration control of auto-negotiation, speed, and duplex-mode selection. For a software reset, register bit ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 8 Hardware Configuration Settings 5.5 Establishing Link Figure 9 shows an overview of link establishment for the LXT971A PHY. Note: When a link is established by using parallel detection, the ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 9 Link Establishment Overview Disable Auto-Negotiation Go To Forced Settings Done 5.5.1 Auto-Negotiation If not configured for forced operation, the LXT971A PHY attempts to auto-negotiate with its link partner by ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.5.1.2 Manual Next Page Exchange “Next Page Exchange” information is additional information that exceeds the information required by Base Page exchange and that is sent by “Next Pages”. The LXT971A PHY ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 The LXT971A PHY implements the Media Independent Interface (MII) as defined by the IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the LXT971A PHY (TXD), ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 10 Clocking for 10BASE-T TX_CLK RX_CLK XI Figure 11 Clocking for 100BASE-X TX_CLK RX_CLK XI ® Cortina Systems LXT971A Single-Port 10/100 Mbps PHY Transceiver 2.5 MHz during auto-negotiation and 10BASE-T ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 12 Clocking for Link Down Clock Transition RX_CLK TX_CLK 5.6.2 Transmit Enable The MAC must assert TX_EN the same time as the first nibble of preamble and de-assert TX_EN after ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 . Table 14 Carrier Sense, Loopback, and Collision Conditions Speed Duplex Condition Full-Duplex 100 Mbps Half-Duplex Full-Duplex Half-Duplex, 10 Mbps register bit 16 Half-Duplex, register bit 16 ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 13 Loopback Paths LXT97x PHY MII 5.6.7.1 Operational Loopback • Operational loopback is provided for 10 Mbps half-duplex links when register bit 16 Data that the MAC (TXData) ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.7 100 Mbps Operation 5.7.1 100BASE-X Network Operations During 100BASE-X operation, the LXT971A PHY transmits and receives 5-bit symbols across the network link. Figure 14 shows the structure of a standard ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 15 100BASE-TX Data Path Standard Data Flow D0 Parallel to Serial Serial to D3 Parallel Scrambler Bypass Data Flow S0 Parallel to S1 Serial ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 17 100BASE-TX Reception with Invalid Symbol RX_CLK RX_DV RXD<3:0> preamble SFD SFD DA RX_ER 5.7.2 Collision Indication Figure 18 shows normal transmission. Figure 18 100BASE-TX Transmission with No Errors TX_CLK ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.7.3 100BASE-X Protocol Sublayer Operations With respect to the 7-layer communications model, the LXT971A PHY is a Physical Layer 1 (PHY) device. The LXT971A PHY implements the following sublayers of the ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.7.3.1.1 Preamble Handling When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-of-Stream Delimiter (SSD), for the first two nibbles received across the MII. ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 15 4B/5B Coding (Sheet Code Code Type Undefined Undefined Undefined Undefined Undefined INVALID Undefined Undefined Undefined Undefined Undefined Undefined 1. The /I/ ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.7.3.2.3 Carrier Sense For 100BASE-TX and 100BASE-FX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes assertion of carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.7.3.3.4 Programmable Slew Rate Control The LXT971A PHY device supports a programmable slew-rate mechanism whereby one of four pre-selected slew rates can be used. (For details, see Register - Address 30, ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.8.4 10BASE-T Link Integrity Test In 10BASE-T mode, the LXT971A PHY always transmits link pulses. • If the Link Integrity Test function is enabled (the normal configuration), the LXT971A PHY monitors ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 • register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex). Note: When the LXT971A PHY detects incorrect polarity for a 10BASE-T operation, register ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.9.4 LED Pulse Stretching The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. The pulse stretch time is extended further if the event occurs ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 5.10.3 Instruction Register After the state machine resets, the IDCODE instruction is always invoked. The decode logic ensures the correct data flow to the Data registers according to the current instruction. ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 6.0 Application Information 6.1 Magnetics Information The LXT971A PHY requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 22 Typical Twisted-Pair Interface - Switch LXT97x PHY SD/TP_L 1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 23 Typical Twisted-Pair Interface - NIC LXT97x PHY 1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 24 show a typical media independent interface (MII) for the LXT971A PHY. Figure 24 Typical Media Independent Interface MAC 6.3 Fiber Interface The fiber interface consists of an LVPECL transmit ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 25 Typical Interface - LXT971A PHY to 3.3 V Fiber PHY TPFON TPFOP LXT97x PHY SD/TP_L TPFIN TPFIP 1. Refer to the manufacturers’ recommendations for termination circuitry. The following occurs ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 26 Typical Interface LXT971A PHY Fiber PHY TPFON TPFOP LXT97x PHY SD/TP_L TPFIN TPFIP 1. Refer to the manufacturers’ recommendations for termination circuitry. 2. See Figure 26 ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 27 (a close-up view of PHY and a PECL-to-PECL logic translator. Figure 27 Typical Interface - LXT971A PHY to Triple PECL-to-PECL Logic Translator 0.01 μ Ω PECL ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 7.0 Electrical Specifications This chapter includes test specifications for the LXT971A PHY. These specifications are guaranteed by test except where noted “by design”. Caution: Exceeding the absolute maximum rating values may ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 22 Recommended Operating Conditions (Sheet Parameter Recommended supply voltage VCC current - 100 BASE-TX VCC current - 10 BASE-T VCC current - 100 BASE-FX Sleep Mode Hard ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 25 I/O Characteristics - REFCLK/XI and XO Pins Parameter Input Low Voltage Input High Voltage Input Clock Frequency Tolerance 2 Input Clock Duty Cycle Input Capacitance 1. Typical values are ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 28 100BASE-TX PHY Characteristics (Sheet Parameter Duty cycle distortion Overshoot/Undershoot Jitter (measured differentially) 1. Typical values are at 25 °C and are for design aid only, not ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 31 10BASE-T Link Integrity Timing Characteristics Parameter Time Link Loss Receive Link Pulse Link Min Receive Timer Link Max Receive Timer Link Transmit Period Link Pulse Width 1. Typical values ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 28 100BASE-TX Receive Timing - 4B Mode 0 ns TPFI CRS RX_DV RXD[3:0] RX_CLK COL Table 33 100BASE-TX Receive Timing Parameters - 4B Mode Parameter RXD[3:0], RX_DV, RX_ER RX_CLK High ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 29 100BASE-TX Transmit Timing - 4B Mode TXCLK TX_EN TXD[3:0] TPFO CRS Table 34 100BASE-TX Transmit Timing Parameters - 4B Mode Parameter TXD[3:0], TX_EN, TX_ER TX_CLK High TXD[3:0], TX_EN, TX_ER ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 30 100BASE-FX Receive Timing TPFI CRS RX_DV RXD[3:0] RX_CLK COL Table 35 100BASE-FX Receive Timing Parameters Parameter RXD[3:0], RX_DV, set up to RX_CLK High RXD[3:0], RX_DV, RX_ER from RX_CLK High ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 31 100BASE-FX Transmit Timing TXCLK TX_EN TXD[3:0] TPFO CRS Table 36 100BASE-FX Transmit Timing Parameters Parameter TXD[3:0], TX_EN, TX_ER TX_CLK High TXD[3:0], TX_EN, TX_ER hold from TX_CLK High TX_EN sampled ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 32 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS TPFI COL Figure 33 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS TPI COL ® Cortina Systems LXT971A Single-Port 10/100 Mbps ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 37 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High TPFIP RXD out (Rx latency) CRS asserted to ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 34 10BASE-T Transmit Timing TX_CLK t TXD, TX_EN, TX_ER CRS TPFO Table 38 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 35 10BASE-T Jabber and Unjabber Timing TX_EN TXD COL Table 39 10BASE-T Jabber and Unjabber Timing Parameter Maximum transmit time Unjabber time 1. Typical values are at 25 °C and ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 37 Auto-Negotiation and Fast Link Pulse Timing TPFOP Figure 38 Fast Link Pulse Timing TPFOP Table 41 Auto-Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 39 MDIO Input Timing MDC MDIO Figure 40 MDIO Output Timing MDC MDIO Table 42 MDIO Timing Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 41 Power-Up Timing VCC MDIO, and so on Table 43 Power-Up Timing Parameter Voltage threshold 2 Power Up delay 1. Typical values are at 25° C and are for design ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 44 RESET_L Pulse Width and Recovery Timing Parameter RESET_L pulse width RESET_L recovery delay2 1. Typical values are at 25° C and are for design aid only, not guaranteed, and ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 8.0 Register Definitions - IEEE Base Registers This chapter includes definitions for the IEEE base registers used by the LXT971A PHY. Section 9.0, Register Definitions - Product-Specific Registers additional product-specific LXT971A ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 46 Control Register - Address 0, Hex 0 Bit Name 0.15 Reset 0.14 Loopback 0.13 Speed Selection Auto-Negotiation 0.12 Enable 0.11 Power-Down 0.10 Isolate Restart Auto- 0.9 Negotiation 0.8 Duplex ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 47 MII Status Register #1 - Address 1, Hex 1 Bit Name 100BASE-T4 1.15 Not Supported 100BASE-X Full- 1.14 Duplex 100BASE-X Half- 1.13 Duplex 1.12 10 Mbps Full-Duplex 1.11 10 ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 48 PHY Identification Register 1 - Address 2, Hex 2 Bit Name Note: See Figure 43 for identifier bit mapping. 2.15:0 PHY ID Number Read Only Table ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 50 Auto-Negotiation Advertisement Register - Address 4, Hex 4 Bit Name 4.15 Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved 4.11 Asymmetric Pause 4.10 Pause 4.9 100BASE-T4 100BASE-TX full-duplex ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 51 Auto-Negotiation Link Partner Base Page Ability Register - Address 5, Hex 5 Bit Name 5.15 Next Page 5.14 Acknowledge 5.13 Remote Fault 5.12 Reserved 5.11 Asymmetric Pause 5.10 Pause ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 52 Auto-Negotiation Expansion - Address 6, Hex 6 Bit Name 6.15:6 Reserved 6.5 Base Page Parallel 6.4 Detection Fault Link Partner Next 6.3 Page Able 6.2 Next Page Able 6.1 ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 54 Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 Bit Name 8.15 Next Page (NP) 8.14 Acknowledge (ACK) 8.13 Message Page (MP) Acknowledge 2 8.12 (ACK2) ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 9.0 Register Definitions - Product-Specific Registers This chapter includes definitions of product-specific LXT971A PHY registers that are defined in accordance with the IEEE 802.3 standard for adding unique device functions. (For ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 56 Configuration Register - Address 16, Hex 10 (Sheet Bit Name TP Loopback 16.8 (10BASE-T) CRS Select 16.7 (10BASE-T) 16.6 Sleep Mode 16.5 PRE_EN 16.4:3 Sleep Timer ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 57 Status Register #2 - Address 17, Hex 11 (Sheet Bit Name 17.9 Duplex Mode 17.8 Auto-Negotiation Auto-Negotiation 17.7 Complete 17.6 Reserved 17.5 Polarity 17.4 Pause 17:3 ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 58 Interrupt Enable Register - Address 18, Hex 12 Bit Name 18. Reserved 15:9 18.8 Reserved 18.7 ANMSK 18.6 SPEEDMSK 18.5 DUPLEXMSK 18.4 LINKMSK 18.3 Reserved 18.2 Reserved 18.1 INTEN ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 59 Status Change Register - Address 19, Hex 13 (Sheet Bit Name 19.4 LINKCHG 19.3 Reserved 19.2 MDINT_L 19.1 Reserved 19.0 Reserved 1. R/W = Read/Write, RO ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 60 LED Configuration Register - Address 20, Hex 14 (Sheet Bit Name LED1 20.15:12 Programming bits LED2 20.11:8 Programming bits 1. R/W = Read /Write ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 60 LED Configuration Register - Address 20, Hex 14 (Sheet Bit Name LED3 20.7:4 Programming bits 5 20.3:2 LEDFREQ PULSE- 20.1 STRETCH 20.0 Reserved 1. R/W = ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Table 61 Digital Configuration Register - Address 26, Hex 1A (Sheet Bit Name 26.5:4 Reserved 26.3 Reserved 26.2:0 Reserved 1. R/W = Read /Write Read Only ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 10.0 Package Specifications Figure 44 PBGA Package Specification 64-Ball Plastic Ball Grid Array Package Note: The package figure is generic and used only to demonstrate package dimensions. 0.20 (4X) 7.00 ± ...
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LXT971A PHY Datasheet 249414, Revision 5.2 13 September 2007 Figure 45 LQFP Package Specifications 64-Pin Low-Profile Quad Flat Pack Note: The package figure is generic and Millimeters Dim Min Max A – 1.60 A 0.05 0. 1.35 1.45 ...
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For additional product and ordering information: www.cortina-systems.com ~ End of Document ~ TM ...