ELLXT971ABE.A4-870479 Cortina Systems Inc, ELLXT971ABE.A4-870479 Datasheet - Page 36

• Manufacturer Part Number: ELLXT971ABE.A4-870479
• Description: TXRX FAST ETH EXT TEMP 64-PBGA
• Manufacturer: Cortina Systems Inc

Specifications of ELLXT971ABE.A4-870479

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1004

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
5.5.1.2
5.5.1.3
5.5.2
5.6
Cortina Systems
Manual Next Page Exchange
“Next Page Exchange” information is additional information that exceeds the information
required by Base Page exchange and that is sent by “Next Pages”. The LXT971A PHY
fully supports the IEEE 802.3 standard method of negotiation through the Next Page
exchange.
The Next Page exchange uses Register 7 to send information and Register 8 to receive it.
Next Page exchange occurs only if both ends of the link partners advertise their ability to
exchange Next Pages. register bit 6.1 is used to make manual next page exchange easier
for software. This register bit is cleared when a new negotiation occurs, preventing the
user from reading an old value in Register 6 and assuming there is valid information in
Registers 5 and 8.
Controlling Auto-Negotiation
When auto-negotiation is controlled by software, Cortina recommends the following steps:
Parallel Detection
In parallel with auto-negotiation, the LXT971A PHY also monitors for 10 Mbps Normal
Link Pulses (NLP) or 100 Mbps Idle symbols. If either symbol is detected, the device
automatically reverts to the corresponding speed in half-duplex mode. Parallel detection
allows the LXT971A PHY to communicate with devices that do not support auto-
negotiation.
When parallel detection resolves a link, the link must be established in half-duplex mode.
According to IEEE standards, the forced link partner cannot be configured to full-duplex. If
the auto-negotiation link partner does not advertise half-duplex capability at the speed of
the forced link partner, link is not established. The IEEE Standard prevents full-duplex-to-
half-duplex link connections.
MII Operation
This section includes the following topics:
®
1. After power-up, power-down, or reset, the power-down recovery time (specified in
2. Set the Auto-Negotiation Advertisement register bits.
3. Enable auto-negotiation. (Set MDIO register bit 0.12 = 1.)
4. To ensure proper operation, enable or restart auto-negotiation as soon as possible
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LXT971A Single-Port 10/100 Mbps PHY Transceiver
Table 44, RESET_L Pulse Width and Recovery Timing, on page
exhausted before proceeding.
after writing to Register 4.
Section 5.6.1, MII Clocks
Section 5.6.2, Transmit Enable
Section 5.6.3, Receive Data Valid
Section 5.6.4, Carrier Sense
Section 5.6.5, Error Signals
Section 5.6.6, Collision
Section 5.6.7, Loopback
77) must be
5.6 MII Operation
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