ELLXT971ABE.A4-870479 Cortina Systems Inc, ELLXT971ABE.A4-870479 Datasheet - Page 33

• Manufacturer Part Number: ELLXT971ABE.A4-870479
• Description: TXRX FAST ETH EXT TEMP 64-PBGA
• Manufacturer: Cortina Systems Inc

Specifications of ELLXT971ABE.A4-870479

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1004

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
5.4.3
5.4.4
Table 13
Cortina Systems
1. L = Low, and H = High. For LED/CFG pin assignments, see
Auto-Neg.
Disabled
Enabled
Desired Mode
(Mbps)
Speed
10/100
Only
100
100
10
Reset
The LXT971A PHY provides both hardware and software resets, each of which manage
differently the configuration control of auto-negotiation, speed, and duplex-mode
selection.
For a software reset, register bit 0.15 = 1. For register bit definitions used for software
reset, see
For pin settings used during a hardware reset, see
Settings. During a hardware reset, configuration settings for auto-negotiation and speed
are read in from pins, and register information is unavailable for 1 ms after de-assertion of
the reset.
Hardware Configuration Settings
The LXT971A PHY provides a hardware option to set the initial device configuration. As
listed in
for which provide control bits.
Hardware Configuration Settings
As shown in
circuits.
®
• During a software reset, bit settings in
• During a software reset, registers are available for reading. To see when the LXT971A
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Register - Address 4, Hex 4, on page 82
configuration pins. Instead, the bit settings revert to the values that were read in
during the last hardware reset. Therefore, any changes to pin values made since the
last hardware reset are not detected during a software reset.
PHY has completed reset, the reset bit can be polled (that is, register bit 0.15 = 0).
Full or Half
Half Only
Full/Half
Duplex
Table 13,
Half
Half
Half
Full
Full
Table 46, Control Register - Address 0, Hex 0, on page
Figure
H
H
H
H
1
L
L
L
L
Settings
LED/CFG
the hardware option uses the hardware configuration pins, the settings
8, the LED drivers can operate as either open-drain or open-source
Pin
H
H
H
H
2
L
L
L
L
H
H
H
H
1
3
L
L
L
L
Auto-
Neg.
0.12
0
1
Control Register
Speed
0.13
Section 3.0, Ball and Pin Assignments
0
0
1
1
1
1
1
1
Table 50, Auto-Negotiation Advertisement
Duplex
Full-
are not re-read from the LXT971A PHY
0.8
Resulting register bit Values
1
0
1
0
1
0
1
0
Section 5.4.4, Hardware Configuration
BASE-TX
Duplex
Full-
100
4.8
Auto-Negotiation Advertisement
0
1
0
1
BASE-
Auto-Negotiation
100
4.7
Advertisement
TX
1
1
1
1
79.
Register
N/A
BASE-T
Duplex
Full-
4.6
10
5.4 Initialization
0
0
0
1
BASE-T
Page 33
4.5
10
0
0
1
1