ELLXT971ABE.A4-870479 Cortina Systems Inc, ELLXT971ABE.A4-870479 Datasheet - Page 53

• Manufacturer Part Number: ELLXT971ABE.A4-870479
• Description: TXRX FAST ETH EXT TEMP 64-PBGA
• Manufacturer: Cortina Systems Inc

Specifications of ELLXT971ABE.A4-870479

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1004

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
5.10.3
Table 16
5.10.4
Table 17
5.10.5
Table 18
Cortina Systems
Instruction Register
After the state machine resets, the IDCODE instruction is always invoked. The decode
logic ensures the correct data flow to the Data registers according to the current
instruction.
Table 17
Valid JTAG Instructions
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used
for the serial shift stage and the parallel output stage.
operation.
BSR Mode of Operation
Device ID Register
Table 18
continuation characters, see the specification update for the LXT971A PHY.
Device ID Register
®
EXTEST
IDCODE
SAMPLE
HIGHZ
CLAMP
BYPASS
1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored. The JEDEC ID is FE
Bits 31:28
Mode
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Version
1
2
3
4
XXXX
(1111 1110), which becomes 111 1110.
Name
lists valid LXT971A PHY JTAG instructions.
lists the bits for the Device ID register. For the current version of the JEDEC
Part ID (Hex)
System Function
Bits 27:12
1111 1111 1110 1000
1111 1111 1111 1000
1111 1111 1100 1111
1111 1111 1111 1110
1111 1111 1110 1111
1111 1111 1111 1111
Description
03CB
Capture
Update
Shift
Code
JEDEC Continuation Characters
External Test
ID Code Inspection
Sample Boundary
Force Float
Control Boundary to 1/0
Bypass Scan
Bits 11:8
Description
0000
Table 17
Test
Normal
Normal
Normal
Test
Normal
lists the four BSR modes of
Mode
5.10 Boundary Scan (JTAG
JEDEC ID
111 1110
Bits 7:1
1149.1) Functions
BSR
ID REG
BSR
Bypass
Bypass
Bypass
1
Data Register
Reserved
Bit 0
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