WM8510GEDS/V Wolfson Microelectronics, WM8510GEDS/V Datasheet
WM8510GEDS/V
Specifications of WM8510GEDS/V
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WM8510GEDS/V Summary of contents
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... Limiter IP PGA IP BOOST/MIX Wind Noise Filters SIDETONE CONTROL PLL INTERFACE 25k 25k 5k 250k 250k http://www.wolfsonmicro.com/enews/ WM8510 rejection W WM8510 MONO OUT -10dB or +0dB SPKOUTP - (-R) = L+R -10dB or +0dB SPKOUTN SPKR PGA Production Data, September 2008, Rev 4.5 Copyright ©2008 Wolfson Microelectronics plc ...
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WM8510 DESCRIPTION .......................................................................................................1 BLOCK DIAGRAM .................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 TERMINOLOGY ............................................................................................................ 8 SIGNAL TIMING REQUIREMENTS .......................................................................9 SYSTEM CLOCK TIMING ............................................................................................. 9 AUDIO ...
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... Production Data PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8510GEDS/V -40°C to +85°C WM8510GEDS/RV -40°C to +85°C Note: Reel Quantity = 2,000 w PACKAGE MOISTURE SENSITIVITY 28-lead SSOP (Pb-free) 28-lead SSOP (Pb-free, tape and reel) WM8510 PACKAGE BODY LEVEL TEMPERATURE o MSL3 260 ...
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WM8510 PIN DESCRIPTION PIN NAME 1 VMID 2 MICN 3 MICP 4 MICBIAS AVDD 7 AGND 8 AGND 9 DCVDD 10 DBVDD 11 DGND 12 ADCDAT 13 DACDAT 14 FRAME Digital Input/Output 15 BCLK Digital Input/Output 16 ...
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Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...
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WM8510 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, T otherwise stated. PARAMETER Microphone Inputs (MICN, MICP) Full-scale Input Signal Level (Note 1) – note this changes with AVDD Mic PGA equivalent input ...
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Production Data Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, T otherwise stated. PARAMETER MIC2 Analogue Input Full-scale Input Signal Level (0dB) – note this scales with AVDD Input Resistance Input Capacitance Digital to Analogue ...
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WM8510 TERMINOLOGY 1. MICN input only in single ended microphone configuration. Maximum input signal to MICP without distortion is -3dBV. 2. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up ...
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Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T PARAMETER System Clock Timing Information MCLK System clock cycle time MCLK duty cycle AUDIO INTERFACE TIMING – MASTER MODE ...
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WM8510 Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge ...
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Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T MCLK = ...
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WM8510 CONTROL INTERFACE TIMING – 2-WIRE MODE t 3 SDIN t 6 SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T 256fs, 24-bit data, unless otherwise stated. PARAMETER Program ...
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Production Data DEVICE DESCRIPTION INTRODUCTION The WM8510 is a low power audio codec combining a high quality mono audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device are anticipated to include VoIP ...
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WM8510 AUDIO INTERFACES The WM8510 has a standard audio interface, to support the transmission of audio data to and from the chip. This interface wire standard audio interface which supports a number of audio data formats including ...
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Production Data Figure 6 Microphone Input PGA Circuit (switch positions shown are for pseudo-differential mic input) REGISTER ADDRESS R44 Input Control The input PGA is enabled by the INPGAEN register bit. REGISTER ADDRESS R2 Power Management 2 w BIT LABEL ...
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WM8510 INPUT PGA VOLUME CONTROL The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the MICN input to the PGA output and from the MIC2 amplifier to the PGA output are ...
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Production Data In mixer mode (MIC2MODE=1) the on-chip input resistor is bypassed, this allows the user to sum in multiple inputs with the use of external resistors. variations through this path from part to part due to the variation of ...
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WM8510 The MICP path to the BOOST stage is controlled by the MICP2BOOSTVOL[2:0] register bits. When MICP2BOOSTVOL=000 this input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB ...
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Production Data VMID Figure 9 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8510 uses a multi-bit, oversampled sigma-delta ADC channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. ...
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WM8510 The ADC is enabled by the ADCEN register bit. REGISTER ADDRESS R2 Power management 2 Table 8 ADC Enable The polarity of the output signal can also be changed under software control using the ADCPOL register bit. With ADCOSR=0 ...
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Production Data PROGRAMMABLE NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. These coefficients should be converted to 2’s complement numbers to determine the register ...
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WM8510 fb = 100 48000 Hz = π π b − − NFn_A0 = -a0 x 213 = -8085 (rounded ...
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Production Data DIGITAL ADC VOLUME CONTROL The output of the ADCs can be digitally attenuated over a range from –127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: Gain = 0.5 x ...
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WM8510 REGISTER ADDRESS R33 (21h) ALC Control 2 w BIT LABEL DEFAULT 3:0 ALCLVL 1011 [3:0] (-12dB) 8 ALCZC 0 (zero cross off) 7:4 ALCHLD 0000 [3:0] (0ms) Production Data DESCRIPTION ALC target – sets signal level at ADC input ...
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Production Data REGISTER ADDRESS R34 (22h) ALC Control 3 Table 14 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing ...
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WM8510 NORMAL MODE In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing the gain of the PGA. The following diagram shows an example of this. Figure 11 ALC Normal Mode Operation w ...
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Production Data LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC ...
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WM8510 NORMAL MODE ALCMODE = 0 (Normal Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 0 (Normal Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 15 ALC ...
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Production Data LIMITER MODE ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 16 ...
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WM8510 MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is ...
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Production Data ALCMIN 000 001 010 011 100 101 110 111 Table 19 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or ...
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WM8510 Figure 14 ALCLVL w Production Data PD, Rev 4.5 ,September 2008 32 ...
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Production Data Input Signal PGA Gain Output of PGA Figure 15 ALC Hold Time ALCHLD Table 21 ALC Hold Time Values w t HOLD t (s) HOLD 0000 0 0001 2.67ms 0010 5.34ms 0011 10.7ms 0100 21.4ms 0101 42.7ms 0110 ...
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WM8510 PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped ...
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Production Data Figure 16 ALC Operation Above Noise Gate Threshold w WM8510 PD, Rev 4.5, September 2008 35 ...
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WM8510 Figure 17 Noise Gate Operation OUTPUT SIGNAL PATH The WM8510 output signal paths consist of digital application filters, up-sampling filters, a Hi-Fi DAC, analogue mixers, speaker and mono output drivers. The digital filters and DAC are enabled by bit ...
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Production Data Figure 18 DAC Digital Filter Path The analogue output from the DAC can then be mixed with the MIC2 analogue input and the ADC analogue input. The mix is fed to the output drivers, SPKOUTP/N, and MONOOUT. MONOOUT: ...
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WM8510 The WM8510 also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will ramp back up to the digital gain setting. This function is enabled by default. To ...
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Production Data The limiter has a programmable upper threshold which is close to 0dB. Referring to Table 30, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. LIMATK register bits) until the signal ...
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WM8510 REGISTER ADDRESS R24 DAC digital limiter control 1 R25 DAC digital limiter control 2 Table 28 DAC Digital Limiter Control w BIT LABEL DEFAULT 3:0 LIMATK 0010 7:4 LIMDCY 0011 8 LIMEN 0 3:0 LIMBOOST 0000 6:4 LIMLVL 000 ...
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Production Data ANALOGUE OUTPUTS The WM8510 has a single MONO output and two outputs SPKOUTP and SPOUTN for driving a mono BTL speaker. These analogue output stages are supplied from SPKVDD and are capable of driving up to 1.5V rms ...
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WM8510 REGISTER ADDRESS R49 Output control R1 Power management 1 Table 29 Output Boost Control SPKBOOST/ MONOBOOST Table 30 Output Boost Stage Details SPKOUTP/SPKOUTN OUTPUTS The SPKOUT pins can drive a single bridge tied 8 Ω speaker or two headphone ...
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Production Data REGISTER ADDRESS R54 Speaker volume control Table 32 SPKOUT Volume Control ZERO CROSS TIMEOUT A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output PGAs the gain will automatically ...
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WM8510 REGISTER ADDRESS R56 Mono mixer control R40 Bypass path attenuation control Table 35 Mono Mixer Control ENABLING THE OUTPUTS Each analogue output of the WM8510 can be separately enabled or disabled. The analogue mixer associated with each output has ...
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Production Data REGISTER ADDRESS R49 Table 37 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 21. This buffer can be enabled using the BUFIOEN register bit. If ...
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WM8510 OUTPUT SWITCH When the device is configured with a 2-wire interface the CSB/GPIO pin can be used as a switch control input to automatically disable the speaker outputs and enable the mono output. For example when a line is ...
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Production Data HEADPHONE OUTPUT The speaker outputs can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors coupled without any capacitor. Headphone Output using DC Blocking Capacitors: Figure 23 Recommended Headphone Output Configurations When DC ...
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WM8510 DIGITAL AUDIO INTERFACES The audio interface has four pins: • • • • The clock signals BCLK, and FRAME can be outputs when the WM8510 operates as a master, or inputs when slave (see Master and ...
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Production Data Figure 26 Right Justified Audio Interface (assuming n-bit word length mode, the MSB is available on the second rising edge of BCLK following a FRAME transition. The other bits up to the LSB are ...
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WM8510 REGISTER ADDRESS R4 Audio interface control Table 41 Audio Interface Control AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised below. Each audio interface can be controlled individually. Register bit ...
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Production Data REGISTER ADDRESS R6 Clock generation control Table 42 Clock Control LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC ...
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WM8510 REGISTER ADDRESS R5 Companding control Table 43 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: µ-law (where µ=255 for the U.S. and Japan): F(x) ...
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Production Data 120 100 Figure 29 u-Law Companding 120 100 Figure 30 A-Law Companding AUDIO SAMPLE RATES The WM8510 sample rates for the ADC and the DAC are set using the SR register bits. The cutoffs ...
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WM8510 REGISTER ADDRESS R7 Additional control Table 45 Sample Rate Control MASTER CLOCK AND PHASE LOCKED LOOP (PLL) The WM8510 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8510 audio functions ...
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Production Data The PLL frequency ratio EXAMPLE: MCLK=12MHz, required clock = 12.288MHz. R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide the PLL and a selectable divide ...
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WM8510 GENERAL PURPOSE INPUT/OUTPUT The CSB/GPIO pin can be configured to perform a variety of useful tasks by setting the GPIOSEL register bits. The GPIO is only available in 2 wire mode. Note that SLOWCLKEN must be enabled when using ...
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Production Data Figure 32 3-Wire Serial Control Interface 2-WIRE SERIAL CONTROL MODE The WM8510 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address ...
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WM8510 POWER SUPPLIES The WM8510 can use up to four separate power supplies: AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and mono output drivers. AVDD can range from 2.5V to 3.6V and has the ...
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Production Data Power Down (all cases Notes: 1. This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference voltage for all inputs and outputs. This ...
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WM8510 Notes: 1. The analogue input pin charge time, t time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. 2. The analogue input pin discharge time, t capacitor ...
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Production Data SYMBOL t line_midrail_on t line_midrail_off t hp_midrail_on t hp__midrail_off t dacint Table 52 Typical POR Operation (typical values, not tested) Notes: 1. The lineout charge time, t time is dependent upon the value of VMID decoupling capacitor and ...
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WM8510 VMID The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the startup time of the VMID circuit. ...
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Production Data POWER SAVING For minimum power consumption in standby mode, VMIDSEL should not be set to default. Instead, the following sequence of writes should be implemented: 1. R10[ (DACMU=1 0x00 0x00. ...
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WM8510 REGISTER MAP REGISTER B8 ADDR NAME B[15:9] DEC HEX 0 00 Software Reset 1 01 Power manage’t 1 BUFDCOP Power manage’ Power manage’ Audio Interface BCP 5 05 ...
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Production Data REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER BIT LABEL ADDRESS ...
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WM8510 BIT LABEL REGISTER ADDRESS 5 SPKPEN 4 3 MONOMIXEN 2 SPKMIXEN 1 0 DACEN 4 (04h) 8 BCP 7 FRAMEP 6:5 WL 4:3 FMT 2 DACLRSWAP 1 ADCLRSWAP 0 5 (05h) 8:5 4:3 DAC_COMP 2:1 ADC_COMP w DEFAULT DESCRIPTION ...
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Production Data BIT LABEL REGISTER ADDRESS 0 LOOPBACK 6 (06h) 8 CLKSEL 7:5 MCLKDIV 4:2 BCLKDIV (07h) 8:4 3 SLOWCLKEN 8 (08h) 8:6 5:4 OPCLKDIV w DEFAULT DESCRIPTION 0 Digital loopback function 0=No loopback ...
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WM8510 BIT LABEL REGISTER ADDRESS 3 GPIOPOL 2:0 GPIOSEL 9 (09h) 8:0 10 (0Ah) 8:7 6 DACMU 5:4 DEEMPH 3 DACOSR128 2 AMUTE 1 0 DACPOL 11 (0Bh) 8 7:0 DACVOL 12 (0Ch) 8:0 13 (0Dh) 8:0 14 (0Eh) 8 ...
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Production Data BIT LABEL REGISTER ADDRESS 2:1 0 ADCPOL 15 (0Fh) 8 7:0 ADCVOL 24 (18h) 8 LIMEN 7:4 LIMDCY 3:0 LIMATK 25 (19h) 8:7 6:4 LIMLVL w DEFAULT DESCRIPTION 00 Reserved 0 ADC Polarity 0=normal 1=inverted 0 Reserved 11111111 ...
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WM8510 BIT LABEL REGISTER ADDRESS 3:0 LIMBOOST 27 (1Bh) 8 NFU 7 NFEN 6:0 NFA0[13:7] 28 (1Ch) 8 NFU 7 6:0 NFA0[6:0] 29 (1Dh) 8 NFU 7 6:0 NFA1[13:7] 30 (1Eh) 8 NFU 7 6:0 NFA1[6:0] 32 (20h) 8 ALCSEL ...
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Production Data BIT LABEL REGISTER ADDRESS 2:0 ALCMIN 33 (21h) 8 ALCZC 7:4 ALCHLD 3:0 ALCLVL 34 (22h) 8 ALCMODE 7:4 ALCDCY 3:0 ALCATK w DEFAULT DESCRIPTION 000 Set minimum gain of PGA when using ALC: 000=-12dB 001=-6dB 010=0dB 011=+6dB ...
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WM8510 BIT LABEL REGISTER ADDRESS 35 (23h) 8:4 3 NGEN 2:0 NGTH 36 (24h) 8:5 4 PLLPRESCALE 3:0 PLLN[3:0] 37 (25h) 8:6 5:0 PLLK[23:18] 38 (26h) 8:0 PLLK[17:9] 39 (27h) 8:0 PLLK[8:0] 40 (28h) 8:3 2 MONOATTN 1 SPKATTN 0 ...
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Production Data BIT LABEL REGISTER ADDRESS 44 (2Ch) 8 MBVSEL 7:4 3 MIC2MODE 2 MIC2_2INPP GA 1 MICN2INPPGA 0 MICP2INPPGA 45 (2Dh INPPGAZC 6 INPPGAMUTE 5:0 INPPGAVOL 47 (2Fh) 8 PGABOOST 7 6:4 MICP2BOOST VOL 3 w DEFAULT ...
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WM8510 BIT LABEL REGISTER ADDRESS 2:0 MIC2_2BOOST VOL 49 (31h) 8:4 3 MONOBOOST 2 SPKBOOST 1 TSDEN 0 VROI 50 (32h) 8:6 5 MIC2_2SPK 4:2 1 BYP2SPK 0 DAC2SPK 54 (36h SPKZC 6 SPKMUTE 5:0 SPKVOL 56 (38h) ...
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Production Data BIT LABEL REGISTER ADDRESS 6 MONOMUTE 5:3 2 MIC2_2MONO 1 BYP2MONO 0 DAC2MONO w DEFAULT DESCRIPTION 0 MONOOUT Mute Control 0=No mute 1=Output muted. During mute the mono output will output VMID which can be used as a ...
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WM8510 DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation 3 Group Delay ADC High Pass Filter High Pass Filter Corner Frequency DAC Filter Passband Passband Ripple Stopband Stopband Attenuation 3 Group Delay Table 57 Digital Filter ...
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Production Data DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) Figure 36 DAC Digital Filter Frequency Response ADC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency ...
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WM8510 DE-EMPHASIS FILTER RESPONSES -10 0 2000 4000 6000 8000 10000 Frequency (Hz) Figure 40 De-emphasis Frequency Response (32kHz -10 ...
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Production Data HIGHPASS FILTER The WM8510 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter applications mode the filter ...
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WM8510 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 50 Recommended External Components w Production Data PD, Rev 4.5 ,September 2008 80 ...
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Production Data PACKAGE DIAGRAM DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm Dimensions Symbols (mm) MIN NOM A ----- A 0. 1.65 1. 0.22 c 0.09 D 9.90 ...
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... WM8510 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...