A3P400-FGG484 Actel, A3P400-FGG484 Datasheet - Page 11

• Manufacturer Part Number: A3P400-FGG484
• Description: FPGA - Field Programmable Gate Array 400K System Gates
• Manufacturer: Actel

Specifications of A3P400-FGG484

• Processor Series: A3P400
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 194
• Data Ram Size: 55296
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 400 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1-3 • VersaTile Configurations
X1
X2
X3
LUT-3 Equivalent
LUT-3
Refer to
User Nonvolatile FlashROM
Actel ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM
can be used in diverse system applications:
The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks (except in the A3P015 and A3P030 devices), as in
security keys stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The Actel ProASIC3 development software solutions, Libero
Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential
programming files for applications requiring a unique serial number in each part. Another feature allows
the inclusion of static data for system version control. Data for the FlashROM can be generated quickly
and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support
is also included to allow for easy programming of large numbers of parts with differing FlashROM
contents.
SRAM and FIFO
ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their
north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory
configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent
read and write ports that can be configured with different bit widths on each port. For example, data can
be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be
initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in A3P015
and A3P030 devices).
•
•
•
•
•
•
•
•
Y
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
Figure 1-3
for VersaTile configurations.
D-Flip-Flop with Clear or Set
Data
CLK
CLR
D-FF
R e v i s i o n 9
Y
®
Enable D-Flip-Flop with Clear or Set
Integrated Design Environment (IDE) and
Enable
Data
CLK
CLR
ProASIC3 Flash Family FPGAs
D-FF
Y
1 -5