A3P400-FGG484 Actel, A3P400-FGG484 Datasheet - Page 45

• Manufacturer Part Number: A3P400-FGG484
• Description: FPGA - Field Programmable Gate Array 400K System Gates
• Manufacturer: Actel

Specifications of A3P400-FGG484

• Processor Series: A3P400
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 194
• Data Ram Size: 55296
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 400 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-34 • I/O Short Currents I
The length of time an I/O can withstand I
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 110°C, the short current condition would have to be sustained for more than three
months to cause a reliability concern. The I/O design does not contain any short circuit protection, but
such protection would only be needed in extremely prolonged stress conditions.
Table 2-35 • Duration of Short Circuit Event before Failure
Table 2-36 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
Notes:
1. T
2. Applicable to 3.3 V LVCMOS Wide Range. I
Temperature
–40°C
0°C
25°C
70°C
85°C
100°C
110°C
Input Buffer
LVTTL/LVCMOS
LVDS/B-LVDS/
M-LVDS/LVPEC
L
*
The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is
low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The
longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends
signal integrity evaluation/characterization of the system to ensure that there is no excessive noise
coupling into input signals.
for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as
specified in the JESD-8B specification.
J
= 100°C
Applicable to Standard I/O Banks
Input Rise/Fall Time (min.)
No requirement
No requirement
2
OSH
/I
OSL
OSH
R e v i s i o n 9
OSL
/I
Drive Strength
OSL
/I
OSH
Input Rise/Fall Time (max.)
100 µA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
2 mA
events depends on the junction temperature. The
dependent on the I/O buffer drive strength selected
Time before Failure
10 ns *
10 ns *
> 20 years
> 20 years
> 20 years
6 months
3 months
5 years
2 years
I
OSL
ProASIC3 Flash Family FPGAs
TBD
27
27
54
54
18
18
37
37
11
22
16
(mA)*
20 years (110°C)
10 years (100°C)
Reliability
I
OSH
TBD
25
25
51
51
16
16
32
32
17
13
9
(mA)*
2- 31