A3P400-FGG484 Actel, A3P400-FGG484 Datasheet - Page 84

• Manufacturer Part Number: A3P400-FGG484
• Description: FPGA - Field Programmable Gate Array 400K System Gates
• Manufacturer: Actel

Specifications of A3P400-FGG484

• Processor Series: A3P400
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 194
• Data Ram Size: 55296
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 400 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3 DC and Switching Characteristics
OUTBUF_LVPECL
Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-93 • Minimum and Maximum DC Input and Output Levels
Table 2-94 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-95 • LVPECL
2- 70
DC Parameter
VCCI
VOL
VOH
VIL, VIH
V
V
V
V
Input Low (V)
1.64
*
Speed Grade
Std.
–1
–2
Note:
ODIFF
OCM
ICM
IDIFF
Measuring point = V
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Timing Characteristics
Supply Voltage
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
Output Low Voltage
Output High Voltage
Input Low, Input High Voltages
FPGA
trip.
See
t
DOUT
0.66
0.56
0.49
Description
Table 2-22 on page 2-22
N
P
Bourns Part Number: CAT16-PC4F12
100 Ω
100 Ω
1.80
1.53
1.34
J
t
DP
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Input High (V)
187 W
for a complete table of trip points.
1.94
0.625
1.762
Min.
0.96
1.01
300
1.8
R e visio n 9
0
Z
Z
0
0
3.0
= 50 Ω
= 50 Ω
Max.
1.27
1.98
2.57
2.11
0.97
0.04
0.04
0.03
t
3.3
DIN
100 Ω
0.625
1.762
Table 2-6 on page 2-6
Min.
1.06
1.92
1.01
300
0
3.3
P
N
Max.
1.43
2.28
0.97
1.98
2.57
3.6
1.40
1.19
1.05
t
Measuring Point* (V)
PY
FPGA
+
0.625
1.762
–
Min.
1.30
2.13
1.01
Cross point
300
0
for derating values.
3.6
INBUF_LVPECL
Figure
Max.
1.57
2.41
0.97
1.98
2.57
3.9
Units
ns
ns
ns
2-13. The
Units
mV
V
V
V
V
V
V
V