A3P400-FGG484 Actel, A3P400-FGG484 Datasheet - Page 46

• Manufacturer Part Number: A3P400-FGG484
• Description: FPGA - Field Programmable Gate Array 400K System Gates
• Manufacturer: Actel

Specifications of A3P400-FGG484

• Processor Series: A3P400
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 194
• Data Ram Size: 55296
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 400 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3 DC and Switching Characteristics
Table 2-37 • Minimum and Maximum DC Input and Output Levels
Table 2-38 • Minimum and Maximum DC Input and Output Levels
2- 32
3.3 V LVTTL /
3.3 V LVCMOS
Drive Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. I
2. I
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
3.3 V LVTTL /
3.3 V LVCMOS
Drive Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
1. I
2. I
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
larger when operating outside recommended ranges
larger when operating outside recommended ranges
IL
IH
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < V
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
is the input leakage current per I/O pin over recommended operating conditions V
Applicable to Advanced I/O Banks
Applicable to Standard Plus I/O Banks
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Min.
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
V
VIL
VIL
Max.
Max.
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
V
V
Min.
Min.
V
V
2
2
2
2
2
2
2
2
2
2
2
2
2
VIH
V
IH
Max.
Max.
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
V
Max.
Max.
VOL
VOL
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
V
R e visio n 9
VOH
VOH
Min.
Min.
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
V
V
mA mA
I
24 24
mA
OL
12 12
16 16
I
2
6
4
8
OL
12
16
2
4
6
8
I
OH
2
6
4
8
mA
I
OH
12
16
2
6
4
8
Max.
mA
I
109
127
181
IH
OSL
27
27
54
54
Max.
mA
I
109
109
OSL
27
27
54
54
< V
3
3
IN
< VCCI. Input current is
Max.
IN
I
mA
Max.
I
mA
103
103
OSH
103
132
268
OSH
25
51
25
51
25
25
51
51
< VIL.
3
3
µA
I
µA
10
10
I
IL
10
10
10
10
IL
10
10
10
10
10
10
10
1
4
1
4
µA
µA
I
I
10
10
IH
IH
10
10
10
10
10
10
10
10
10
10
10
2
2
4
4