STM32F103ZCT7 STMicroelectronics, STM32F103ZCT7 Datasheet - Page 86

• Manufacturer Part Number: STM32F103ZCT7
• Description: MCU ARM 32BIT 256KB FLSH 144LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F103ZCT7

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 112
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 21x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Electrical characteristics
5.3.14
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Figure 42. I/O AC characteristics definition
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under ambient temperature and V
Table
Table 48.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
Figure 43. Recommended NRST pin protection
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the V
V
V
V
V
V
NF(NRST)
IH(NRST)
IL(NRST)
Symbol
F(NRST)
hys(NRST)
to the series resistance must be minimum
Table
R
10.
PU
48. Otherwise the reset will not be taken into account by the device.
(1)
(1)
(1)
(1)
PU
External
reset circuit
NRST pin characteristics
(see
NRST Input low level voltage
NRST Input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
EXT ERNAL
OUTPUT
ON 50pF
Maximum frequency is achieved if (t r + t f ) 2/3)T and if the duty cycle is (45-55%)
Table
(1)
0.1 µF
45).
Parameter
t r(I O)out
NRST
Doc ID 14611 Rev 7
(2)
(~10% order)
10%
V DD
50%
when loaded by 50pF
R PU
90%
(2)
STM32F103xC, STM32F103xD, STM32F103xE
.
DD
supply voltage conditions summarized in
Conditions
V
T
10%
IN
Table 48

50%
V
Filter
SS
90%
t r(I O)out
STM32F10xxx
are derived from tests
IL(NRST)
Internal Reset
–0.5
Min
300
30
2
max level specified in
Typ
200
40
V
DD
ai14132c
Max
100
0.8
50
+0.5
ai14131
Unit
mV
k
ns
ns
V