STM32F103ZCT7 STMicroelectronics, STM32F103ZCT7 Datasheet - Page 88

• Manufacturer Part Number: STM32F103ZCT7
• Description: MCU ARM 32BIT 256KB FLSH 144LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F103ZCT7

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 112
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 21x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Electrical characteristics
5.3.16
88/123
Communications interfaces
I
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
The STM32F103xC, STM32F103xD and STM32F103xE performance line I
meets the requirements of the standard I
restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When
configured as open-drain, the PMOS connected between the I/O pin and V
but is still present.
The I
characteristics
and SCL) .
Table 50.
1. Guaranteed by design, not tested in production.
2. f
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
2
t
C interface characteristics
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
su(STO)
higher than 4 MHz to achieve the maximum fast mode I
period of SCL signal.
undefined region of the falling edge of SCL.
t
t
t
su(STA)
h(SDA)
PCLK1
r(SDA)
h(STA)
r(SCL)
f(SDA)
f(SCL)
C
2
C characteristics are described in
b
must be higher than 2 MHz to achieve the maximum standard mode I
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
I
2
C characteristics
for more details on the input/output alternate function characteristics (SDA
Table
Parameter
10.
Doc ID 14611 Rev 7
Standard mode I
PCLK1
Table
2
C communication protocol with the following
Min
250
0
STM32F103xC, STM32F103xD, STM32F103xE
4.7
4.0
4.0
4.7
4.0
4.7
(3)
frequency and V
50. Refer also to
2
C frequency.
Table 50
1000
Max
300
400
2
C
(1)
are derived from tests
20 + 0.1C
DD
Fast mode I
Section 5.3.13: I/O port
2
Min
100
C frequency. It must be
0
1.3
0.6
0.6
0.6
0.6
1.3
supply voltage conditions
(4)
b
DD
2
2
C
900
C interface
Max
300
300
400
(1)(2)
is disabled,
(3)
Unit
s
s
pF
µs
ns
µs