STM32F103ZCT7 STMicroelectronics, STM32F103ZCT7 Datasheet - Page 93

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STM32F103ZCT7

Manufacturer Part Number
STM32F103ZCT7
Description
MCU ARM 32BIT 256KB FLSH 144LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F103ZCT7

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
112
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 21x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32F103ZCT7
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM32F103xC, STM32F103xD, STM32F103xE
Table 53.
1. Based on design simulation and/or characterization results, not tested in production.
2. Depends on f
DuCy(SCK)
f
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
r(CK)
f(CK)
v(WS)
h(WS)
su(WS)
h(WS)
w(CKH)
w(CKL)
su(SD_MR)
su(SD_SR)
h(SD_MR)
h(SD_SR)
v(SD_ST)
h(SD_ST)
v(SD_MT)
h(SD_MT)
c(CK)
Symbol
(1)
(1)
(1)
(1)
(1)
(1)
(1)(2)
(1)(2)
(1)
(1)(2)
(1)(2)
(1)
(1)
(1)
I
2
PCLK
S characteristics
I2S slave input clock duty
cycle
I
I
WS valid time
WS hold time
WS setup time
WS hold time
CK high and low time
Data input setup time
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
2
2
S clock frequency
S clock rise and fall time
. For example, if f
Parameter
PCLK
=8 MHz, then T
Slave mode
Master mode (data: 16 bits,
Audio frequency = 48 kHz)
Slave mode
Capacitive load C
Master mode
Master mode
Slave mode
Slave mode
Master f
frequency = 48 kHz
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter (after enable
edge)
Slave transmitter (after enable
edge)
Master transmitter (after enable
edge)
Master transmitter (after enable
edge)
Doc ID 14611 Rev 7
PCLK
PCLK
Conditions
= 1/f
= 16 MHz, audio
PLCLK
L
= 50 pF
=125 ns.
I2S2
I2S3
I2S2
I2S3
1.522
312.5
Min
345
6.5
1.5
0.5
30
11
0
3
2
0
4
0
2
0
0
Electrical characteristics
1.525
Max
70
6.5
18
8
3
MHz
Unit
ns
%
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