ISL54100AHDMI-EVALZ Intersil, ISL54100AHDMI-EVALZ Datasheet - Page 11

• Manufacturer Part Number: ISL54100AHDMI-EVALZ
• Description: EVAL BOARD FOR ISL54100AHDMI
• Manufacturer: Intersil

Specifications of ISL54100AHDMI-EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Listing
0x04
0x05
0x06
ADDRESS
Termination Control (0x00)
Output Options (0x00)
Data Output Drive (0x00)
REGISTER (DEFAULT VALUE)
(Continued)
11
ISL54100A, ISL54101A, ISL54102A
BIT(S)
3:0
7:4
0
1
2
3
4
5
6
7
0
1
2
3
Data Termination A
Data Termination B
Data Termination C
Data Termination D
Clk Termination A
Clk Termination B
Clk Termination C
Clk Termination D
Tri-state Clock
Outputs
Tri-state Data
Outputs
Invert Output
Polarity
Reverse Output
Order
Transmit Current
Transmit
Pre-emphasis
FUNCTION NAME
0: Channel A TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel A TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
0: Channel B TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel B TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
0: Channel C TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel C TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
0: Channel D TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel D TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
0: Channel A TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel A TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
0: Channel B TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel B TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
0: Channel C TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel C TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
0: Channel D TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel D TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
0: Normal Operation
1: Clock outputs tri-stated (allows another chip to drive the
output clock pins)
0: Normal Operation
1: Data outputs tri-stated (allows another chip to drive the
output data pins)
0: Normal Operation
1: The polarity of the TMDS data outputs is inverted
(+ becomes -, - becomes +). TMDS clock unchanged.
0: Normal Operation
1: CH0 data is output on CH2 and CH2 data is output on
CH0. No change to CH1.
Transmit Drive Current for data signals, adjustable in
0.125mA steps. Clock current is fixed at 10mA.
0x0: 10mA
0x8: 11mA
0xF: 11.875mA
Drive boost (in 0.125mA steps) added during first half of
each bit period for data signals. Clock signals do not have
pre-emphasis.
0x0: 0mA
0x8: 1mA
0xF: 1.875mA
DESCRIPTION
June 17, 2008
FN6725.0