ISL54100AHDMI-EVALZ Intersil, ISL54100AHDMI-EVALZ Datasheet - Page 18

• Manufacturer Part Number: ISL54100AHDMI-EVALZ
• Description: EVAL BOARD FOR ISL54100AHDMI
• Manufacturer: Intersil

Specifications of ISL54100AHDMI-EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The ISL5410xA has a 7-bit address on the serial bus,
determined by the ADDR0-ADDR6 bits. This allows up to
128 ISL5410xAs to be independently controlled by the same
serial bus.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 14).
The ISL5410xA continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met. The host then
transmits the 7-bit serial address plus a R/W bit, indicating if
the next transaction will be a Read (R/W = 1) or a Write (R/W
= 0). If the address transmitted matches that of any device
on the bus, that device must respond with an
ACKNOWLEDGE (Figure 15).
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be
written to or read from the slave. Communication with the
selected device in the selected direction (read or write) is
ended by a STOP command, where SDA rises while SCL is
high (Figure 14), or a second START command, which is
FROM TRANSMITTER
FROM RECEIVER
DATA OUTPUT
DATA OUTPUT
SCL FROM
HOST
SDA
SCL
SDA
SCL
18
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
START
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
ISL54100A, ISL54101A, ISL54102A
FIGURE 14. VALID START AND STOP CONDITIONS
DATA STABLE
START
1
DATA CHANGE
commonly used to reverse data direction without
relinquishing the bus.
Data on the serial bus must be valid for the entire time SCL
is high (Figure 16). To achieve this, data being written to the
ISL5410xA is latched on a delayed version of the rising edge
of SCL. SCL is delayed and deglitched inside the ISL5410xA
for three crystal clock periods (120ns for a 25MHz crystal) to
eliminate spurious clock pulses that could disrupt serial
communication.
When the contents of the ISL5410xA are being read, the
SDA line is updated after the falling edge of SCL, delayed
and deglitched in the same manner.
Configuration Register Write
Figure 17 shows two views of the steps necessary to write
one or more words to the Configuration Register.
Configuration Register Read
Figure 18 shows two views of the steps necessary to read
one or more words from the Configuration Register.
DATA STABLE
8
STOP
ACKNOWLEDGE
9
June 17, 2008
FN6725.0