ISL54100AHDMI-EVALZ Intersil, ISL54100AHDMI-EVALZ Datasheet - Page 14

• Manufacturer Part Number: ISL54100AHDMI-EVALZ
• Description: EVAL BOARD FOR ISL54100AHDMI
• Manufacturer: Intersil

Specifications of ISL54100AHDMI-EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Tx Pre-emphasis
The transmit pre-emphasis function sinks additional current
during the first bit after every transition, increasing the slew
rate for a given capacitance, and helping to maintain the
slew rate when using longer/higher capacitance cables.
Pre-emphasis is controlled by register 0x06 bits 7:4, and
ranges from a minimum of 0mA (no pre-emphasis) to
1.875mA (max pre-emphasis).
PLL Bandwidth
The 2-bit PLL Bandwidth register controls the loop
bandwidth of the PLL used to recover the incoming clock
signal. The default 4MHz setting works well in most
applications, however a lower bandwidth of 1MHz has
proven to work just as well with good TMDS sources and
slightly better with marginal sources.
Power-down
The chip can be placed in a Power-down mode when not in
use to conserve power. Setting the Power-down bit (register
0x02 bit 5) to a 1 or pulling the PD input pin high places the
chip in a minimal power consumption mode, turning off all
TMDS outputs and disconnecting all TMDS inputs. Serial I/O
stays operational in PD mode. Note that the PD pin must be
low during power-on in order to initialize the I
Note: When exiting Power-down, a termination resistor
Recalibration cycle must be run to re-trim the termination
resistors (see register 0x03[7]).
Power Dissipation and Supply Current
Due to the large number of TMDS inputs and outputs, a
significant amount of current flows into and out of the
SL5410x. This makes calculating the total power dissipation
of the ISL5410xA slightly more complicated than simply
multiplying the supply current by the supply voltage.
The supply current measurement includes the current
flowing through all the active TMDS termination resistors.
This current is supplied by the ISL5410xA's V
only 15% of it (0.5V*10mA per TMDS pair) is dissipated as
power inside the ISL5410xA. The majority of the power
(2.8V * 10mA per active TMDS pair) is dissipated in the
TMDS transmitter driving the ISL5410xA. Likewise, the
ISL5410xA dissipates 85% of the power generated by the
current from the external receiver attached to the
ISL5410xA's Tx pins. Any worst-case on-chip power
dissipation calculation needs to account for this.
Inter-Pair (Channel-to-Channel) Skew
The read pointers for Channel 0, 1, and 2 of the FIFO that
follows the CDR all have the same clock, so all 3 channels
transition within a few picoseconds of each other - there is
essentially no skew between the transitions of the three
channels.
14
ISL54100A, ISL54101A, ISL54102A
2
D
C interface.
supplies, but
However the FIFO read pointers may be positioned up to 2
bits apart relative to each other, introducing a random, fixed
channel-to-channel skew of skew of 1 or (much less
frequently) 2 bits. The random skew is introduced whenever
there is a discontinuity in the input signal (typically a video
mode change or a new mux channel selection). After the
CDRs and PLL lock, the skew is fixed until the next
discontinuity. This adds up to 2 bits of skew in addition to any
incoming skew, as shown in the following examples.
Figure 2 shows an input (the top three signals) with essentially
no skew. After the ISL5410xA locks on to the signal, there
may be 1 bit of skew on the output, as shown in Figure 2.
When there is pre-existing skew on the input, the ISL5410xA
can add up to 2 bits to the channel-to-channel skew. In the
example in Figure 3, the incoming red channel has 2.3 bits of
skew relative to the incoming green and blue. The FIFO’s
quantization (worst case) increases the total skew to 4.0 bits.
While increasing skew is not desirable, DVI and HDMI
receivers are required to have a minimum of 6 bits of inter-pair
skew tolerance, so the addition of 2 bits of skew is only a
problem with the most pathological cables and transmitters. It
OUTPUT SKEW
(1 bit – 615ps at
OUTPUT SKEW
162.5Mpixels/s)
162.5Mpixels/s)
(4 bits/2.5ns at
in this example)
INPUT SKEW
(2.3 bits/1.4ns
INPUT SKEW
(none, in this
FIGURE 2. MAXIMUM ADDITIONAL INTERCHANNEL SKEW
FIGURE 3. MAXIMUM ADDITIONAL INTERCHANNEL SKEW
example)
Bit 5
Bit 7
Bit 7
Bit 4
Bit 7
Bit 8
Bit 7
Bit 7
Bit 7
Bit 6
Bit 7
Bit 7
FOR INPUTS WITH NO OR LITTLE SKEW
FOR INPUTS WITH MODERATE TO LARGE
SKEW
Bit 4
Bit 3
Bit 7
Bit 6
Bit 6
Bit 6
Bit 5
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 3
Bit 4
Bit 5
Bit 5
Bit 2
Bit 5
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 2
Bit 3
Bit 4
Bit 4
Bit 1
Bit 4
Bit 5
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 1
Bit 0
Bit 4
Bit 3
Bit 3
Bit 3
Bit 2
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 0
Bit 2
Bit 2
Bit 2
Bit 1
Bit 2
Bit 2
Bit 2
Bit 2
Bit 9
Bit 2
Bit 3
Bit 9
Bit 8
Bit 0
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 8
Bit 0
Bit 0
Bit 0
Bit 9
Bit 0
Bit 0
Bit 0
Bit 0
Bit 7
Bit 0
Bit 1
Bit 7
June 17, 2008
Bit 9
Bit 9
Bit 9
Bit 8
Bit 9
Bit 9
Bit 9
Bit 9
Bit 6
Bit 9
Bit 0
FN6725.0
Bit 6
Bit 7
Bit 5
Bit 9
Bit 8
Bit 8
Bit 8
Bit 8
Bit 8
Bit 8
Bit 8
Bit 8
Bit
B
B
B
B
B
B
B
B
B
B
B