ADSP-21161NKCA-100 Analog Devices Inc, ADSP-21161NKCA-100 Datasheet - Page 16

• Manufacturer Part Number: ADSP-21161NKCA-100
• Description: IC, FLOAT-PT DSP, 32BIT, 100MHZ, MBGA225
• Manufacturer: Analog Devices Inc
• Series: SHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCA-100

• No. Of Bits: 32 Bit
• Frequency: 100MHz
• Supply Voltage: 1.8V
• Embedded Interface Type: HPI, SPI
• No. Of I/o's: 12
• Supply Voltage Range: 1.71V To 1.89V, 3.13V To 3.47V
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADSP-21161NKCA100

ADSP-21161N
Table 2. Pin Function Descriptions (Continued)
1
Pin
CLKDBL
CLKOUT
RESET
RSTOUT
TCK
TMS
TDI
TDO
TRST
EMU
V
V
AVDD
AGND
GND
NC
RSTOUT exists only for silicon revisions 1.2 and greater.
DDINT
DDEXT
1
Type
I
O/T
I/A
O
I
I/S
I/S
O
I/A
O (O/D)
P
P
P
G
G
Function
Crystal Double Mode Enable. This pin is used to enable the 2 clock double circuitry, where CLKOUT can
be configured as either 1 or 2 the rate of CLKIN. This CLKIN double circuit is primarily intended to be used
for an external crystal in conjunction with the internal clock generator and the XTAL pin. The internal clock
generator when used in conjunction with the XTAL pin and an external crystal is designed to support up to
a maximum of 27.5 MHz external crystal frequency. CLKDBL can be used in XTAL mode to generate a 55 MHz
input into the PLL. The 2 clock mode is enabled (during RESET low) by tying CLKDBL to GND, otherwise it is
connected to V
MHz core clock rates and a 55 MHz CLKOUT operation when CLK_CFG0=0, CLK_CFG1=0 and CLKDBL=0.
This pin can also be used to generate different clock rate ratios for external clock oscillators as well. The
possible clock rate ratio options (up to 110 MHz) for either CLKIN (external clock oscillator) or XTAL (crystal
input) are shown in
MHz core (instruction clock) rate and a 25 MHz CLKOUT (external port) clock rate. See also
Page
other external clock sources, the maximum CLKIN frequency is 55 MHz.
Local Clock Out. CLKOUT is 1 or 2 and is driven at either 1 or 2 the frequency of CLKIN frequency by the
current bus master. The frequency is determined by the CLKDBL pin. This output is three-stated when the
ADSP-21161N is not the bus master or when the host controls the bus (HBG asserted). A keeper latch on the
DSP’s CLKOUT pin maintains the output at the level it was last driven. This latch is only enabled on the ADSP-
21161N with ID2–0=00x.
If CLKDBL enabled, CLKOUT=2 CLKIN
If CLKDBL disabled, CLKOUT=1 CLKIN
Note: CLKOUT is only controlled by the CLKDBL pin and operates at either 1 CLKIN or 2 CLKIN.
Do not use CLKOUT in multiprocessing systems. Use CLKIN instead.
Processor Reset. Resets the ADSP-21161N to a known state and begins execution at the program memory
location specified by the hardware reset vector address. The RESET input must be asserted (low) at power-up.
Reset Out. When RSTOUT is asserted (low), this pin indicates that the core blocks are in reset. It is deasserted
4080 cycles after RESET is deasserted indicating that the PLL is stable and locked.
Test Clock (JTAG). Provides a clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k internal pull-up
resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held
low for proper operation of the ADSP-21161N. TRST has a 20 k internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21161N Analog Devices DSP Tools product line of JTAG
emulators target board connector only. EMU has a 50 k internal pull-up resistor.
Core Power Supply. Nominally +1.8 V dc and supplies the DSP’s core processor (14 pins).
I/O Power Supply. Nominally +3.3 V dc. (13 pins).
Analog Power Supply. Nominally +1.8 V dc and supplies the DSP’s internal PLL (clock generator). This pin
has the same specifications as V
see Power Supplies on Page 9.
Analog Power Supply Return.
Power Supply Return. (26 pins).
Do Not Connect. Reserved pins that must be left open and unconnected. (4 pins).
21. Note: When using an external crystal, the maximum crystal frequency cannot exceed 27.5 MHz. For all
DDEXT
Rev. B | Page 16 of 60 | November 2009
for 1 clock mode. For example, this enables the use of a 27.5 MHz crystal to enable 110
Table 3 on Page
DDINT
, except that added filtering circuitry is required.
17. An 8:1 ratio enables the use of a 12.5 MHz crystal to generate a 100
For more information,
Figure 12 on