ADSP-21161NKCA-100 Analog Devices Inc, ADSP-21161NKCA-100 Datasheet - Page 37

• Manufacturer Part Number: ADSP-21161NKCA-100
• Description: IC, FLOAT-PT DSP, 32BIT, 100MHZ, MBGA225
• Manufacturer: Analog Devices Inc
• Series: SHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCA-100

• No. Of Bits: 32 Bit
• Frequency: 100MHz
• Supply Voltage: 1.8V
• Embedded Interface Type: HPI, SPI
• No. Of I/o's: 12
• Supply Voltage Range: 1.71V To 1.89V, 3.13V To 3.47V
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADSP-21161NKCA100

Asynchronous Read/Write — Host to ADSP-21161N
Use these specifications for asynchronous host processor
accesses of an ADSP-21161N, after the host has asserted CS and
HBR (low). After HBG is returned by the ADSP-21161N, the
host can drive the RD and WR pins to access the
ADSP-21161N’s IOP registers. HBR and HBG are assumed low
Table 22. Read Cycle
Table 23. Write Cycle
1
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
Only when slave write FIFO is full.
SADRDL
HADRDH
WRWH
DRDHRDY
DRDHRDY
SDATRDY
DRDYRDL
RDYPRD
HDARWH
SCSWRL
HCSWRH
SADWRH
HADWRH
WWRL
WRWH
DWRHRDY
SDATWH
HDATWH
DRDYWRL
RDYPWR
CS Low Setup Before WR Low
CS Low Hold After WR High
Address Setup Before WR High
Address Hold After WR High
WR Low Width
RD/WR High Width
WR High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before WR High
Data Hold After WR High
REDY (O/D) or (A/D) Low Delay After WR/CS Low
REDY (O/D) or (A/D) Low Pulsewidth for Write
Address Setup and CS Low Before RD Low
Address Hold and CS Hold Low After RD
RD/WR High Width
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
Data Valid Before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay After RD Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable After RD High
Rev. B | Page 37 of 60 | November 2009
1
1
for this timing. Although the DSP will recognize HBR asserted
before reset, a HBG will not be returned by the DSP until after
reset is deasserted and the DSP completes bus synchronization.
Note: Host internal memory access is not supported.
Min
0
2
3.5
0
0
2
1.5t
2
Min
0
0
6
2
t
3.5
0
5
4
12
CCLK
CCLK
Max
10
6
Max
11
ADSP-21161N
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns