ADSP-21161NKCA-100 Analog Devices Inc, ADSP-21161NKCA-100 Datasheet - Page 32

no-image

ADSP-21161NKCA-100

Manufacturer Part Number
ADSP-21161NKCA-100
Description
IC, FLOAT-PT DSP, 32BIT, 100MHZ, MBGA225
Manufacturer
Analog Devices Inc
Series
SHARCr
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-21161NKCA-100

No. Of Bits
32 Bit
Frequency
100MHz
Supply Voltage
1.8V
Embedded Interface Type
HPI, SPI
No. Of I/o's
12
Supply Voltage Range
1.71V To 1.89V, 3.13V To 3.47V
Rohs Status
RoHS non-compliant
Interface
Host Interface, Link Port, Serial Port
Clock Rate
100MHz
Non-volatile Memory
External
On-chip Ram
128kB
Voltage - I/o
3.30V
Voltage - Core
1.80V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
225-MBGA, 225-Mini-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ADSP-21161NKCA100

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21161NKCA-100
Manufacturer:
ADI
Quantity:
2
Part Number:
ADSP-21161NKCA-100
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-21161NKCA-100
Manufacturer:
AD
Quantity:
1 000
Part Number:
ADSP-21161NKCA-100
Manufacturer:
ADI
Quantity:
85
Part Number:
ADSP-21161NKCA-100
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADSP-21161N
Synchronous Read/Write — Bus Master
Use these specifications for interfacing to external memory sys-
tems that require CLKIN, relative to timing or for accessing a
slave ADSP-21161N (in multiprocessor memory space). When
accessing a slave ADSP-21161N, these switching characteristics
Table 18. Synchronous Read/Write — Bus Master
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
SSDATI
HSDATI
SACKC
HACKC
DADDO
HADDO
DRDO
DWRO
DRWL
DDATO
HDATO
WRITE CYCLE
READ CYCLE
ACK
RD
DATA
WR
DATA (OUT)
CLKIN
MSx,
(IN)
ADDRESS
(IN)
BRST
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Setup Before CLKIN
ACK Hold After CLKIN
Address, MSx, BMS, BRST, Delay After CLKIN
Address, MSx, BMS, BRST, Hold After CLKIN
RD High Delay After CLKIN
WR High Delay After CLKIN
RD/WR Low Delay After CLKIN
Data Delay After CLKIN
Data Hold After CLKIN
t
t
DRWL
DRWL
t
DDATO
t
DADDO
Figure 23. Synchronous Read/Write — Bus Master
Rev. B | Page 32 of 60 | November 2009
must meet the slave's timing requirements for synchronous
read/writes (see
Page
master) timing requirements for data and acknowledge setup
and hold times.
33). The slave ADSP-21161N must also meet these (bus
t
SACKC
Min
5.5
1
0.5t
1
1.5
0.25t
0.25t
0.25t
1.5
CCLK
CCLK
CCLK
CCLK
t
SSDATI
t
+3
HADDO
–1
–1
–1
Synchronous Read/Write — Bus Slave on
t
t
DRDO
DWRO
Max
10
0.25t
0.25t
0.25t
12.5
t
HACKC
t
t
HSDATI
HDATO
CCLK
CCLK
CCLK
+9
+9
+9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for ADSP-21161NKCA-100