ADSP-21161NKCA-100 Analog Devices Inc, ADSP-21161NKCA-100 Datasheet - Page 30

• Manufacturer Part Number: ADSP-21161NKCA-100
• Description: IC, FLOAT-PT DSP, 32BIT, 100MHZ, MBGA225
• Manufacturer: Analog Devices Inc
• Series: SHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCA-100

• No. Of Bits: 32 Bit
• Frequency: 100MHz
• Supply Voltage: 1.8V
• Embedded Interface Type: HPI, SPI
• No. Of I/o's: 12
• Supply Voltage Range: 1.71V To 1.89V, 3.13V To 3.47V
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADSP-21161NKCA100

ADSP-21161N
Memory Write — Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN except for ACK pin requirements listed in footnote 1 of
Table 17. Memory Write — Bus Master
1
2
3
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) × t
H = t
HI = t
I = t
For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,
The falling edge of MSx, BMS is referenced.
See
DAAK
DSAK
SAKC
HAKC
DAWH
DAWL
WW
DDWH
DWHA
DWHD
DATRWH
WWR
DDWR
WDE
ACK must be driven low (deasserted) by t
met for both assertion and deassertion of ACK signal.
Example System Hold Time Calculation on Page 55
CKOP
CKOP
CKOP
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
ACK Delay from Address, Selects
ACK Delay from WR Low
ACK Setup to CLKIN
ACK Hold After CLKIN
Address, Selects to WR Deasserted
Address, Selects to WR Low
WR Pulsewidth
Data Setup Before WR High
Address Hold After WR Deasserted
Data Hold After WR Deasserted
Data Disable After WR Deasserted
WR High to WR, RD, DMAGx Low
Data Disable Before WR or RD Low
WR Low to Data Enabled
DAAK
1
, t
1
DSAK
1
, or t
2
for calculation of hold times given capacitive and dc loads.
SAKC
Rev. B | Page 30 of 60 | November 2009
. For the second and subsequent cycles of an asynchronous external memory access, the t
1, 2
3
2
CKOP
.
Min
0.5t
1
t
t
t
0.25t
0.25t
0.25t
0.5t
0.25t
–0.25t
0.25t
CKOP
CKOP
CKOP
CCLK
CCLK
– 0.5t
–0.25t
– 0.25t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
Table
the bus master accessing external memory space in asynchro-
nous access mode.
+3
– 1.25+HI
– 1+H
– 1+H
– 2+H
– 3+I
– 3
– 1
CCLK
CCLK
CCLK
17. These specifications apply when the ADSP-21161N is
– 1+W
– 13.5+W
– 3+W
Max
t
t
0.25t
CKOP
CKOP
–0.5t
–0.75t
CCLK
+2.5+H
CCLK
CCLK
–12+W
–11+W
SAKC
and t
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HAKC
must be