ADSP-21161NKCA-100 Analog Devices Inc, ADSP-21161NKCA-100 Datasheet - Page 55

• Manufacturer Part Number: ADSP-21161NKCA-100
• Description: IC, FLOAT-PT DSP, 32BIT, 100MHZ, MBGA225
• Manufacturer: Analog Devices Inc
• Series: SHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCA-100

• No. Of Bits: 32 Bit
• Frequency: 100MHz
• Supply Voltage: 1.8V
• Embedded Interface Type: HPI, SPI
• No. Of I/o's: 12
• Supply Voltage Range: 1.71V To 1.89V, 3.13V To 3.47V
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADSP-21161NKCA100

OUTPUT DRIVE CURRENTS
Figure 38
ers of the ADSP-21161N. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The DSP is tested for output enable, disable, and hold time.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time t
the point when a reference signal reaches a high or low voltage
level to the point when the output has reached a specified high
or low trip point, as shown in the Output Enable/Disable dia-
gram
enabled, the measurement value is that of the first pin to start
driving.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high-impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by V is dependent on the capacitive load, C
the load current, I
following equation:
The output disable time t
and t
val from when the reference signal switches to when the output
voltage decays V from the measured output high or output low
voltage. t
V equal to 0.5 V.
DECAY
(Figure
–10
–20
–30
–40
–50
–60
–80
80
60
50
40
30
20
10
0
0
DECAY
shows typical I-V characteristics for the output driv-
V
as shown in
DDEXT
39). If multiple pins (such as the data bus) are
is calculated with test loads C
0.5
t
= 3.47V, –40°C
DECAY
V
V
L
DDEXT
Figure 38. Typical Drive Currents
. This decay time can be approximated by the
DDEXT
SWEEP (V
1.0
= (C
= 3.47V, –40°C
Figure
= 3.3V, +25°C
DIS
V
DDEXT
L
DDEXT
is the difference between t
1.5
V)/I
39. The time t
V
= 3.13V, +105°C
) VOLTAGE – V
DDEXT
L
2.0
= 3.3V, +25°C
ENA
2.5
is the interval from
V
DDEXT
MEASURED
L
and I
3.0
= 3.13V, +105°C
Rev. B | Page 55 of 60 | November 2009
L
, and with
is the inter-
MEASURED
3.5
L
and
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the ADSP-21161N’s output voltage
and the input threshold for the device requiring the hold time. A
typical V will be 0.4 V. C
line), and I
line). The hold time will be t
time (i.e., t
REFERENCE
(MEASURED)
(MEASURED)
SIGNAL
V
V
OUTPUT
OUTPUT
OH
OL
t
INPUT
DIS
PIN
TO
OR
DATRWH
L
Measurements (Except Output Enable/Disable)
OUTPUT STOPS DRIVING
is the total leakage or three-state current (per data
Figure 41. Voltage Reference Levels for AC
Figure 40. Equivalent Device Loading for AC
DECAY
1.5V
Measurements (Includes All Fixtures)
for the write cycle).
Figure 39. Output Enable/Disable
using the equation given above. Choose V
t
MEASURED
V
V
OH
OL
t
DECAY
VOLTAGE TO BE APPROXIMATELY 1.5V.
L
(MEASURED) + V
(MEASURED) – V
is the total bus capacitance (per data
30pF
DECAY
TEST CONDITIONS CAUSE THIS
HIGH IMPEDANCE STATE.
plus the minimum disable
50
ADSP-21161N
t
ENA
OUTPUT STARTS DRIVING
2.0V
1.0V
1.5V
1.5V
(MEASURED)
(MEASURED)
V
V
OH
OL