ADSP-21161NKCA-100 Analog Devices Inc, ADSP-21161NKCA-100 Datasheet - Page 21

• Manufacturer Part Number: ADSP-21161NKCA-100
• Description: IC, FLOAT-PT DSP, 32BIT, 100MHZ, MBGA225
• Manufacturer: Analog Devices Inc
• Series: SHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCA-100

• No. Of Bits: 32 Bit
• Frequency: 100MHz
• Supply Voltage: 1.8V
• Embedded Interface Type: HPI, SPI
• No. Of I/o's: 12
• Supply Voltage Range: 1.71V To 1.89V, 3.13V To 3.47V
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADSP-21161NKCA100

Table 7. CLKOUT and CCLK Clock Generation Operation
1
POWER DISSIPATION
Total power dissipation has two components: one due to inter-
nal circuitry and one due to the switching of external output
drivers.
Internal power dissipation depends on the instruction execution
sequence and the data operands involved. Using the current
specifications (I
Electrical Characteristics
operation information in
the ADSP-21161N’s internal power supply (V
rent for a specific application, according to the following
formula:
Timing Requirements
CLKIN
CLKOUT
PLLICLK
CCLK
t
t
t
t
t
t
where:
CK
CCLK
LCLK
SCLK
SDK
SPICLK
LR = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by LxCLKD)
SR = serial port-to-core clock ratio (wide range, determined by CLKDIV)
SDCKR = SDRAM-to-Core Clock Ratio (1:1 or 1:2, determined by SDCTL register)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPICTL register)
LCLK = Link Port Clock
SCLK = Serial Port Clock
SDK = SDRAM Clock
SPICLK = SPI Clock
+ % Peak I
% Peak I
% High I
% Low I
= I
(CRYSTAL OSCILLATOR
DDINPEAK
DD
DD
DDINT
DD
DD
-
-
-
INLOW
-
IDLE
INPEAK
(QUARTZ CRYSTAL
INHIGH
27.5 MHz MAX)
, I
4.2–55 MHz)
on Page 19
Table
DDINHIGH
CLKIN
XTAL
8, the programmer can estimate
, I
MULTIPROCESSING
SYNCHRONOUS EP
DDINLOW
and the current-versus-
SBSRAM
Figure 12. Core Clock and System Clock Relationship to CLKIN
CLOCK DOUBLER
, I
DDIDLE
CLKDBL
DDINT
x1, x2
Description
Input Clock
External Port System Clock
PLL Input Clock
Core Clock
CLKIN Clock Period
(Processor) Core Clock Period
Link Port Clock Period
Serial Port Clock Period
SDRAM Clock Period
SPI Clock Period
Rev. B | Page 21 of 60 | November 2009
) from the
) input cur-
ASYNCHRONOUS EP
CLKOUT
SRAM
HOST
1
CLK_CFG1–0
x2, x3, x4
RATIOS
HARDWARE
INTERRUPT
I/O FLAG
TIMER
PLL
x1, x1/2, x1/3, x1/4
I/O PROCESSOR
SERIAL PORTS
LINK PORTS
x1/8 MAX
x1/2 MAX
SDRAM
x1, x1/2
CORE
Calculation
1/t
1/t
1/t
1/t
1/CLKIN
1/CCLK
(t
(t
(t
(t
SPI
CCLK
CCLK
CCLK
CCLK
CK
CKOP
PLLIN
CCLK
) LR
) SR
) SDCKR
) SPIR
ADSP-21161N