CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 150

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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t
t
t
t
t
t
t
Symbol Figure
Symbol Figure
SCLro
SCLlowo
SCLhigho
SDAfo
SDAro
SDAho
SDAvo
t
t
t
t
t
t
MSKh
t
t
t
t
CLKX
MSKl
t
t
RXS
RXH
RST
X1p
X1h
X2p
X2h
X1l
X2l
t
t
t
t
Ih
Ih
Is
Is
a. Tclk is the actual clock period of the CPU clock used in the system.
b. Guaranteed by design, but not fully tested.
c. Assuming signal’s capacitance up to 400pF.
d. Depends on the signal’s capacitance and the pull-up value. Must be less than 1ms.
e. K is as defined in ACBCTL2.SCLFRQ.
The value of Tclk is system dependent.
The maximum cycle time of 64000ns is for Power Save mode; in active mode, the maximum cycle time is limited to 250ns by
the high frequency oscillator.
77
77
77
77
77
77
81
81
82
80
80
81
81
81
83
83
88
91
91
88
88
91
91
X1 period
X1 high time, external clock
X1 low time, external clock
X2 period
X2 high time, external clock
X2 low time, external clock
Input setup time
ISE
Input hold time
Reset time
Input Pulse Width
Input setup time
Input hold time
CKXn input period
RDXn setup time
RDXn hold time
MICROWIRE Clock High
MICROWIRE Clock Low
SCL signal Rise time
SCL low time
SCL high time
SDA signal Fall time
SDA signal Rise time
SDA hold time
SDA valid time
ISE, NMI, RXD1, RXD2
(synchronous mode)
(synchronous mode)
(synchronous mode)
RXDn (asynchronous mode)
RXDn (asynchronous mode)
a
Description
Description
Table 46 Input Signal Requirements
MICROWIRE / SPI Input Signals
Table 45 Output Signals
USART Input Signals
R.E. X1 to next R.E. X1
At 2V level (Both Edges)
At 0.8V level (Both Edges)
R.E. X2 to next R.E. X2
At 2V level (both edges)
At 0.8V level (both edges)
Before R.E. CLK
After R.E. CLK
Reset active to reset end
Before R.E. CLK
After R.E. CLK
Before F.E. CKX in synchronous mode
After F.E. CKX in synchronous mode
At 2.0V (both edges)
At 0.8V (both edges)
Input Signals
After SCL F.E.
After SCL R.E.
After SCL F.E.
After SCL F.E.
150
Reference
Reference
0.5 Tclk - 500
0.5 Tclk - 500
0.5 Tclk - 4
0.5 Tclk - 4
1*Tclk+13
Min (ns) Max (ns)
K*t
1
K*t
1
Min (ns)
7*t
10,000
e
e
t
4Tclk
SCLfo
200
CLK
CLK
CLK
40
12
12
80
80
0
0
4
2
-
-
-
-
300
7*tCLK+
d
tRD
Max (ns)
-