PIC18F2550T-I/SO Microchip Technology, PIC18F2550T-I/SO Datasheet - Page 124

• Manufacturer Part Number: PIC18F2550T-I/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2550T-I/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD
• Lead Free Status / Rohs Status: Details

PIC18F2455/2550/4455/4550
10.4
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Each of the PORTD pins has a weak internal pull-up. A
single control bit, RDPU (PORTE<7>), can turn on all
the pull-ups. This is performed by setting RDPU. The
weak pull-up is automatically turned off when the port
pin is configured as a digital output or as one of the
other multiplexed peripherals. The pull-ups are
disabled on a Power-on Reset. The PORTE register is
shown in Section 10.5 “PORTE, TRISE and LATE
Registers”.
Three of the PORTD pins are multiplexed with outputs,
P1B, P1C and P1D, of the Enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
DS39632E-page 122
Note:
Note:
PORTD, TRISD and LATD
Registers
PORTD is only available on 40/44-pin
devices.
On a Power-on Reset, these pins are
configured as digital inputs.
PORTD can also be configured as an 8-bit wide
Streaming Parallel Port (SPP). In this mode, the input
buffers are TTL. For additional information on con-
figuration and uses of the SPP, see Section 18.0
“Streaming Parallel Port”.
EXAMPLE 10-4:
CLRF
CLRF
MOVLW
MOVWF
Note:
PORTD
LATD
0CFh
TRISD
When the Enhanced PWM mode is used
with either dual or quad outputs, the MSSP
functions of PORTD are automatically
disabled.
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
INITIALIZING PORTD
© 2009 Microchip Technology Inc.