PIC18F2550T-I/SO Microchip Technology, PIC18F2550T-I/SO Datasheet - Page 215

• Manufacturer Part Number: PIC18F2550T-I/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2550T-I/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD
• Lead Free Status / Rohs Status: Details

19.4.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode and up to
63 addresses in 10-bit mode (see Example 19-3).
The I
masking is used or not. However, when address
masking is used, the I
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking SSPBUF.
In
ADMSK<5:1> (SSPCON2<5:1>) mask the corre-
sponding address bits in the SSPADD register. For any
ADMSK bits that are set (ADMSK<n> = 1), the
corresponding
(SSPADD<n> = x). For the module to issue an address
Acknowledge, it is sufficient to match only on
addresses that do not have an active address mask.
EXAMPLE 19-3:
© 2009 Microchip Technology Inc.
7-bit addressing:
10-bit addressing:
7-Bit
2
C Slave behaves the same way whether address
SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)
ADMSK<5:1>
Addresses Acknowledged : A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
SSPADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since
they are not affected by masking)
ADMSK<5:1>
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh
Address
Address Masking
address
ADDRESS MASKING EXAMPLES
mode,
= 00111
= 00111
2
C slave can Acknowledge
address
bit
is
mask
PIC18F2455/2550/4455/4550
ignored
bits
In 10-Bit Address mode, bits ADMSK<5:2> mask the
corresponding address bits in the SSPADD register. In
addition, ADMSK1 simultaneously masks the two LSbs
of the address (SSPADD<1:0>). For any ADMSK bits
that are active (ADMSK<n> = 1), the corresponding
address bit is ignored (SSPADD<n> = x). Also note
that although in 10-Bit Addressing mode, the upper
address bits reuse part of the SSPADD register bits, the
address mask bits do not interact with those bits. They
only affect the lower address bits.
Note 1: ADMSK1 masks the two Least Significant
2: The two Most Significant bits of the
bits of the address.
address are not affected by address
masking.
DS39632E-page 213