PIC18F2550T-I/SO Microchip Technology, PIC18F2550T-I/SO Datasheet - Page 128

• Manufacturer Part Number: PIC18F2550T-I/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2550T-I/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD
• Lead Free Status / Rohs Status: Details

PIC18F2455/2550/4455/4550
TABLE 10-9:
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
DS39632E-page 126
PORTE
LATE
TRISE
ADCON1
CMCON
SPPCON
SPPCFG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/AN5/
CK1SPP
RE1/AN6/
CK2SPP
RE2/AN7/
OESPP
MCLR/V
RE3
Legend:
Note 1:
Name
Pin
(3)
2:
3:
(3)
PP
(3)
(3)
/
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
These registers or bits are unimplemented on 28-pin devices.
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input
RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.
CLKCFG1 CLKCFG0
RDPU
C2OUT
Bit 7
Function
CK1SPP
CK2SPP
—
—
—
—
OESPP
PORTE I/O SUMMARY
MCLR
RE0
AN5
RE1
AN6
RE2
AN7
RE3
V
(3)
PP
C1OUT
Bit 6
Setting
—
—
—
—
—
TRIS
—
—
—
0
1
1
0
0
1
1
0
0
1
1
0
(1)
(1)
(1)
VCFG1
C2INV
CSEN
OUT
OUT
OUT
OUT
OUT
OUT
Bit 5
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
—
—
—
—
I/O Type
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
CLK1EN
VCFG0
C1INV
Bit 4
—
—
—
—
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
A/D Input Channel 5; default configuration on POR.
SPP clock 1 output (SPP enabled).
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
A/D Input Channel 6; default configuration on POR.
SPP clock 2 output (SPP enabled).
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
A/D Input Channel 7; default configuration on POR.
SPP enable output (SPP enabled).
External Master Clear input; enabled when MCLRE Configuration bit
is set.
High-voltage detection, used for ICSP™ mode entry detection.
Always available regardless of pin mode.
PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
RE3
PCFG3
Bit 3
WS3
CIS
—
—
—
(1,2)
TRISE2
PCFG2
LATE2
RE2
Bit 2
WS2
CM2
—
(3)
Description
SPPOWN
TRISE1
PCFG1
RE1
LATE1
Bit 1
CM1
WS1
© 2009 Microchip Technology Inc.
(3)
TRISE0
PCFG0
SPPEN
RE0
LATE0
Bit 0
CM0
WS0
(3)
on page
Values
Reset
56
56
56
54
55
57
57