PIC18F2550T-I/SO Microchip Technology, PIC18F2550T-I/SO Datasheet - Page 433

• Manufacturer Part Number: PIC18F2550T-I/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2550T-I/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD
• Lead Free Status / Rohs Status: Details

Timer2 .............................................................................. 137
Timer3 .............................................................................. 139
Timing Diagrams
© 2009 Microchip Technology Inc.
TMR1H Register ...................................................... 131
TMR1L Register ....................................................... 131
Use as a Real-Time Clock ....................................... 134
Associated Registers ............................................... 138
Interrupt .................................................................... 138
Operation ................................................................. 137
Output ...................................................................... 138
PR2 Register .................................................... 148, 153
TMR2 to PR2 Match Interrupt .......................... 148, 153
16-Bit Read/Write Mode ........................................... 141
Associated Registers ............................................... 141
Operation ................................................................. 140
Oscillator .......................................................... 139, 141
Overflow Interrupt ............................................ 139, 141
Special Event Trigger (CCP) .................................... 141
TMR3H Register ...................................................... 139
TMR3L Register ....................................................... 139
A/D Conversion ........................................................ 404
Acknowledge Sequence .......................................... 235
Asynchronous Reception (TXCKP = 0,
Asynchronous Transmission (TXCKP = 0,
Asynchronous Transmission, Back to Back
Automatic Baud Rate Calculation ............................ 252
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 258
Baud Rate Generator with Clock Arbitration ............ 229
BRG Overflow Sequence ......................................... 252
BRG Reset Due to SDA Arbitration During
Brown-out Reset (BOR) ........................................... 390
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition
Bus Collision During a Start Condition
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision for Transmit and Acknowledge ........... 236
Capture/Compare/PWM (All CCP Modules) ............ 392
CLKO and I/O .......................................................... 389
Clock Synchronization ............................................. 222
Clock/Instruction Cycle .............................................. 63
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 393
Example SPI Master Mode (CKE = 1) ..................... 394
Example SPI Slave Mode (CKE = 0) ....................... 395
Example SPI Slave Mode (CKE = 1) ....................... 396
External Clock (All Modes Except PLL) ................... 387
Fail-Safe Clock Monitor ............................................ 307
First Start Bit Timing ................................................ 230
TX Not Inverted) .............................................. 257
TX Not Inverted) .............................................. 254
(TXCKP = 0, TX Not Inverted) ......................... 254
Normal Operation ............................................ 258
Start Condition ................................................. 238
Condition (Case 1) ........................................... 239
Condition (Case 2) ........................................... 239
(SCL = 0) ......................................................... 238
(SDA Only) ....................................................... 237
(Case 1) ........................................................... 240
(Case 2) ........................................................... 240
(Master/Slave) ................................................. 401
(Master/Slave) ................................................. 401
PIC18F2455/2550/4455/4550
Full-Bridge PWM Output .......................................... 157
Half-Bridge PWM Output ......................................... 156
High/Low-Voltage Detect Characteristics ................ 384
High-Voltage Detect (VDIRMAG = 1) ...................... 288
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect (VDIRMAG = 0) ....................... 287
Master SSP I
Master SSP I
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 159
PWM Direction Change at Near
PWM Output ............................................................ 148
Repeated Start Condition ........................................ 231
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 259
Slave Synchronization ............................................. 204
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 203
SPI Mode (Slave Mode with CKE = 0) ..................... 205
SPI Mode (Slave Mode with CKE = 1) ..................... 205
SPP Write Address and Data for USB
SPP Write Address and Read Data for
SPP Write Address, Write and Read
Stop Condition Receive or Transmit Mode .............. 235
Streaming Parallel Port (PIC18F4455/4550) ........... 403
Synchronous Reception (Master Mode, SREN) ...... 262
Synchronous Transmission ..................................... 260
Synchronous Transmission (Through TXEN) .......... 261
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 391
Transition for Entry to Idle Mode ............................... 41
Transition for Entry to SEC_RUN Mode .................... 37
Transition for Entry to Sleep Mode ............................ 40
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 397
C Bus Start/Stop Bits ............................................ 397
C Master Mode (7 or 10-Bit Transmission) ........... 233
C Master Mode (7-Bit Reception) ......................... 234
C Slave Mode (10-Bit Reception,
C Slave Mode (10-Bit Reception, SEN = 0) .......... 218
C Slave Mode (10-Bit Reception, SEN = 1) .......... 224
C Slave Mode (10-Bit Transmission) .................... 220
C Slave Mode (7-bit Reception,
C Slave Mode (7-Bit Reception, SEN = 0) ............ 215
C Slave Mode (7-Bit Reception, SEN = 1) ............ 223
C Slave Mode (7-Bit Transmission) ...................... 217
C Slave Mode General Call Address
SEN = 0, ADMSK 01001) ................................ 219
SEN = 0, ADMSK = 01011) ............................. 216
Sequence (7 or 10-Bit Address Mode) ............ 225
Auto-Restart Disabled) .................................... 162
Auto-Restart Enabled) ..................................... 162
100% Duty Cycle ............................................. 159
Timer (OST) and Power-up Timer (PWRT) ..... 390
V
(4 Wait States) ................................................. 193
USB (4 Wait States) ........................................ 193
Data (No Wait States) ...................................... 193
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
DD
Rise > T
2
2
C Bus Data ....................................... 399
C Bus Start/Stop Bits ........................ 399
PWRT
DD
DD
) ............................................ 51
) .......................................... 51
, V
DD
DD
DD
), Case 1 ...................... 50
), Case 2 ...................... 50
Rise T
DD
DS39632E-page 431
,
PWRT
) .............. 50