PN5120A0HN/C2,551 NXP Semiconductors, PN5120A0HN/C2,551 Datasheet
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PN512 Transmission module Rev. 3.6 — 10 March 2011 111336 1. Introduction This document describes the functionality and electrical specifications of the transceiver IC PN512. 2. General description The PN512 is a highly integrated transceiver IC for contactless communication at ...
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... NXP Semiconductors In Card Operation mode, the PN512 transceiver IC is able to answer to a reader/writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN512 generates the digital load modulated signals and in addition with an external circuit the answer can be sent back to the reader/writer. A complete card ...
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... NXP Semiconductors 3. Features and benefits Highly integrated analog circuitry to demodulate and decode responses Buffered output drivers for connecting an antenna with the minimum number of external components Integrated RF Level detector Integrated data mode detector Supports ISO/IEC 14443 A/MIFARE Supports ISO/IEC 14443 B Read/Write modes ...
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... NXP Semiconductors 4. Quick reference data Table 1. Quick reference data Symbol Parameter V analog supply voltage DDA digital supply voltage V DDD V TVDD supply voltage DD(TVDD) V PVDD supply voltage DD(PVDD) V SVDD supply voltage DD(SVDD) I power-down current pd I digital supply current DDD I analog supply current ...
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... NXP Semiconductors 6. Block diagram The analog interface handles the modulation and demodulation of the analog signals according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode communication scheme. The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin. ...
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... NXP Semiconductors SDA/NSS/RX EA I2C D1/ADR_5 SPI, UART, I FIFO CONTROL 64-BYTE FIFO BUFFER CONTROL REGISTER BANK MIFARE CLASSIC UNIT RANDOM NUMBER GENERATOR AMPLITUDE RATING REFERENCE VOLTAGE ANALOG TEST I-CHANNEL MULTIPLEXOR AMPLIFIER AND DIGITAL TO I-CHANNEL ANALOG DEMODULATOR CONVERTER VMID AUX1 AUX2 Fig 2. Detailed block diagram of the PN512 ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 3. Pinning configuration HVQFN32 (SOT617-1) Fig 4. Pinning configuration HVQFN40 (SOT618-1) PN512 Product data sheet COMPANY PUBLIC terminal 1 index area PVDD 3 DVDD DVSS 4 PN512 PVSS 5 6 NRSTPD SIGIN 7 SIGOUT 8 Transparent top view terminal 1 index area PVDD ...
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... NXP Semiconductors 7.2 Pin description Table 3. Pin description HVQFN32 Pin Symbol Type PVDD PWR 3 DVDD PWR 4 DVSS PWR 5 PVSS PWR 6 NRSTPD I 7 SIGIN I 8 SIGOUT O 9 SVDD PWR 10 TVSS PWR 11 TX1 O 12 TVDD PWR 13 TX2 O 14 TVSS PWR 15 AVDD PWR 16 VMID ...
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... NXP Semiconductors Table 4. Pin description HVQFN40 Pin Symbol Type PVDD PWR 6 DVDD PWR 7 DVSS PWR 8 PVSS PWR 9 NRSTPD I 10 SIGIN I 11 SIGOUT O 12 SVDD PWR 13 TVSS PWR 14 TX1 O 15 TVDD PWR 16 TX2 O 17 TVSS PWR 18 AVDD PWR 19 VMID PWR AVSS PWR ...
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... NXP Semiconductors 8. Functional description The PN512 transmission module supports the Read/Write mode for ISO/IEC 14443 A/MIFARE and ISO/IEC 14443 B using various transfer speeds and modulation protocols. PN512 transceiver IC supports the following operating modes: • Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • ...
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... ISO 14443 A and ISO 14443 B. Refer to the ISO 14443 reference documents Identification cards - Contactless integrated circuit cards - Proximity cards (parts 1 to 4). Remark: NXP Semiconductors does not offer a software library to enable design-in of the ISO 14443 B protocol. PN512 Product data sheet ...
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... NXP Semiconductors 8.3 FeliCa reader/writer functionality The FeliCa mode is the general reader/writer to card communication scheme according to the FeliCa specification. The following diagram describes the communication on a physical level, the communication overview describes the physical parameters. Fig 8. FeliCa reader/writer communication diagram Table 6. ...
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... NXP Semiconductors 8.4 NFCIP-1 mode The NFCIP-1 communication differentiates between an active and a Passive Communication mode. • Active Communication mode means both the initiator and the target are using their own RF field to transmit data. • Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active in terms of generating the RF field. • ...
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... NXP Semiconductors 8.4.1 Active communication mode Active communication mode means both the initiator and the target are using their own RF field to transmit data. Fig 10. Active communication mode Table 9. Communication direction Initiator → Target According to Target → Initiator The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol ...
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... NXP Semiconductors 8.4.2 Passive communication mode Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active meaning generating the RF field. host Fig 11. Passive communication mode Table 10. Communication direction Initiator → Target According to Target → Initiator According to The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol ...
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... NXP Semiconductors 8.4.3 NFCIP-1 framing and coding The NFCIP-1 framing and coding in Active and Passive Communication mode is defined in the NFCIP-1 standard. Table 11. Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 8.4.4 NFCIP-1 protocol support The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol refer to the NFCIP-1 standard ...
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... NXP Semiconductors 8.4.6 FeliCa Card operation mode Table 13. Communication direction reader/writer → PN512 PN512 → reader/ writer 9. PN512 register SET 9.1 PN512 registers overview Table 14. Addr (hex) Page 0: Command and Status Page 1: Command PN512 Product data sheet COMPANY PUBLIC FeliCa Card operation mode ...
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... NXP Semiconductors Table 14. Addr (hex Page 2: CFG Page 3: TestRegister PN512 Product data sheet COMPANY PUBLIC PN512 registers overview …continued Register Name Function TxSelReg Selects the internal sources for the antenna driver RxSelReg Selects internal receiver settings RxThresholdReg Selects thresholds for the bit decoder ...
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... NXP Semiconductors Table 14. Addr (hex C-F 9.1.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle bits with same behavior are grouped in common registers. In access conditions are described. Table 15. Abbreviation Behavior r RFU RFT PN512 ...
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... NXP Semiconductors 9.2 Register description 9.2.1 Page 0: Command and status 9.2.1.1 PageReg Selects the register page. Table 16. Access Rights Table 17. Bit 9.2.1.2 CommandReg Starts and stops command execution. Table 18. Access Rights Table 19. Bit PN512 Product data sheet COMPANY PUBLIC PageReg register (address 00h); reset value: 00h, 0000000b ...
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... NXP Semiconductors 9.2.1.3 CommIEnReg Control bits to enable and disable the passing of interrupt requests. Table 20. Access Rights Table 21. Bit PN512 Product data sheet COMPANY PUBLIC CommIEnReg register (address 02h); reset value: 80h, 10000000b IRqInv TxIEn RxIEn IdleIEn r/w r/w r/w Description of CommIEnReg bits ...
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... NXP Semiconductors 9.2.1.4 DivIEnReg Control bits to enable and disable the passing of interrupt requests. Table 22. Access Rights Table 23. Bit PN512 Product data sheet COMPANY PUBLIC DivIEnReg register (address 03h); reset value: 00h, 00000000b IRQPushPull 0 0 SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn r/w RFU ...
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... NXP Semiconductors 9.2.1.5 CommIRqReg Contains Interrupt Request bits. Table 24. Access Rights Table 25. All bits in the register CommIRqReg shall be cleared by software. Bit Symbol 7 Set1 6 TxIRq 5 RxIRq 4 IdleIRq 3 HiAlertIRq 2 LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to 1 ErrIRq 0 TimerIRq PN512 ...
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... NXP Semiconductors 9.2.1.6 DivIRqReg Contains Interrupt Request bits Table 26. Access Rights Table 27. All bits in the register DivIRqReg shall be cleared by software. Bit PN512 Product data sheet COMPANY PUBLIC DivIRqReg register (address 05h); reset value: XXh, 000X00XXb Set2 0 0 SiginActIRq ModeIRq w RFU RFU ...
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... NXP Semiconductors 9.2.1.7 ErrorReg Error bit register showing the error status of the last command executed. Table 28. Access Rights Table 29. Bit [1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible. PN512 Product data sheet COMPANY PUBLIC ErrorReg register (address 06h); reset value: 00h, 00000000b ...
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... NXP Semiconductors 9.2.1.8 Status1Reg Contains status bits of the CRC, Interrupt and FIFO-buffer. Table 30. Access Rights Table 31. Bit PN512 Product data sheet COMPANY PUBLIC Status1Reg register (address 07h); reset value: XXh, X100X01Xb RFFreqOK CRCOk CRCReady Description of Status1Reg bits Symbol Description RFFreqOK Indicates if the frequency detected at the RX pin is in the range of 13 ...
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... NXP Semiconductors 9.2.1.9 Status2Reg Contains status bits of the Receiver, Transmitter and Data mode detector. Table 32. Access Rights Table 33. Bit PN512 Product data sheet COMPANY PUBLIC Status2Reg register (address 08h); reset value: 00h, 00000000b TempSensClear I CForceHS r/w r/w RFU Description of Status2Reg bits ...
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... NXP Semiconductors 9.2.1.10 FIFODataReg In- and output of 64 byte FIFO-buffer. Table 34. Access Rights Table 35. Bit 9.2.1.11 FIFOLevelReg Indicates the number of bytes stored in the FIFO. Table 36. Access Rights Table 37. Bit PN512 Product data sheet COMPANY PUBLIC FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb ...
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... NXP Semiconductors 9.2.1.12 WaterLevelReg Defines the level for FIFO under- and overflow warning. Table 38. Access Rights Table 39. Bit 9.2.1.13 ControlReg Miscellaneous control bits. Table 40. Access Rights Table 41. Bit PN512 Product data sheet COMPANY PUBLIC WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b ...
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... NXP Semiconductors 9.2.1.14 BitFramingReg Adjustments for bit oriented frames. Table 42. Access Rights Table 43. Bit PN512 Product data sheet COMPANY PUBLIC BitFramingReg register (address 0Dh); reset value: 00h, 00000000b StartSend RxAlign w r/w r/w Description of BitFramingReg bits Symbol Description StartSend Set to logic 1, the transmission of data starts. ...
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... NXP Semiconductors 9.2.1.15 CollReg Defines the first bit collision detected on the RF interface. Table 44. Access Rights Table 45. Bit PN512 Product data sheet COMPANY PUBLIC CollReg register (address 0Eh); reset value: XXh, 101XXXXXb Values 0 CollPos AfterColl NotValid r/w RFU r Description of CollReg bits Symbol ...
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... NXP Semiconductors 9.2.2 Page 1: Communication 9.2.2.1 PageReg Selects the register page. Table 46. Access Rights Table 47. Bit PN512 Product data sheet COMPANY PUBLIC PageReg register (address 10h); reset value: 00h, 00000000b UsePage Select 0 0 r/w RFU RFU Description of PageReg bits Symbol Description UsePage Select Set to logic 1, the value of PageSelect is used as register address A5 and A4 ...
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... NXP Semiconductors 9.2.2.2 ModeReg Defines general mode settings for transmitting and receiving. Table 48. Access Rights Table 49. Bit PN512 Product data sheet COMPANY PUBLIC ModeReg register (address 11h); reset value: 3Bh, 00111011b MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff r/w r/w r/w ...
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... NXP Semiconductors 9.2.2.3 TxModeReg Defines the data rate and framing during transmission. Table 50. Access Rights Table 51. Bit PN512 Product data sheet COMPANY PUBLIC TxModeReg register (address 12h); reset value: 00h, 00000000b TxCRCEn TxSpeed r Description of TxModeReg bits Symbol Description TxCRCEn Set to logic 1, this bit enables the CRC generation during data transmission ...
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... NXP Semiconductors 9.2.2.4 RxModeReg Defines the data rate and framing during reception. Table 52. Access Rights Table 53. Bit PN512 Product data sheet COMPANY PUBLIC RxModeReg register (address 13h); reset value: 00h, 00000000b RxCRCEn RxSpeed r Description of RxModeReg bits Symbol Description RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception. ...
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... NXP Semiconductors 9.2.2.5 TxControlReg Controls the logical behavior of the antenna driver pins Tx1 and Tx2. Table 54. Access Rights Table 55. Bit PN512 Product data sheet COMPANY PUBLIC TxControlReg register (address 14h); reset value: 80h, 10000000b InvTx2RF InvTx1RF InvTx2RF On On Off r/w r/w ...
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... NXP Semiconductors 9.2.2.6 TxAutoReg Controls the settings of the antenna driver. Table 56. Access Rights Table 57. Bit PN512 Product data sheet COMPANY PUBLIC TxAutoReg register (address 15h); reset value: 00h, 00000000b AutoRF Force100 Auto OFF ASK WakeUp r/w r/w r/w RFU Description of TxAutoReg bits ...
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... NXP Semiconductors 9.2.2.7 TxSelReg Selects the sources for the analog part. Table 58. Access Rights Table 59. Bit PN512 Product data sheet COMPANY PUBLIC TxSelReg register (address 16h); reset value: 10h, 00010000b DriverSel RFU RFU r/w Description of TxSelReg bits Symbol Description - Reserved for future use. ...
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... NXP Semiconductors Table 59. Bit PN512 Product data sheet COMPANY PUBLIC Description of TxSelReg bits Symbol Description SigOutSel Selects the input for the SIGOUT Pin. Value Description 0000 Tristate 0001 Low 0010 High 0011 TestBus signal as defined by bit TestBusBitSel in register TestSel1Reg. 0100 Modulation signal (envelope) from the internal coder ...
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... NXP Semiconductors 9.2.2.8 RxSelReg Selects internal receiver settings. Table 60. Access Rights Table 61. Bit 9.2.2.9 RxThresholdReg Selects thresholds for the bit decoder. Table 62. Access Rights Table 63. Bit PN512 Product data sheet COMPANY PUBLIC RxSelReg register (address 17h); reset value: 84h, 10000100b UartSel ...
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... NXP Semiconductors 9.2.2.10 DemodReg Defines demodulator settings. Table 64. Access Rights Table 65. Bit PN512 Product data sheet COMPANY PUBLIC DemodReg register (address 19h); reset value: 4Dh, 01001101b AddIQ FixIQ r/w r/w r/w Description of DemodReg bits Symbol Description AddIQ Defines the use of I and Q channel during reception Note: FixIQ has to be set to logic 0 to enable the following settings ...
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... NXP Semiconductors 9.2.2.11 FelNFC1Reg Defines the length of the FeliCa Sync bytes and the minimum length of the received packet. Table 66. Access Rights Table 67. Bit PN512 Product data sheet COMPANY PUBLIC FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b FelSyncLen r/w r/w r/w ...
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... NXP Semiconductors 9.2.2.12 FelNFC2Reg Defines the maximum length of the received packet. Table 68. Access Rights Table 69. Bit PN512 Product data sheet COMPANY PUBLIC FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b 7 6 WaitForSelected ShortTimeSlot r/w r/w Description of FelNFC2Reg bits Symbol Description WaitForSelected Set to logic 1, the AutoColl command is only terminated automatically when: 1 ...
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... NXP Semiconductors 9.2.2.13 MifNFCReg Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating mode. Table 70. Access Rights Table 71. Bit PN512 Product data sheet COMPANY PUBLIC MifNFCReg register (address 1Ch); reset value: 62h, 01100010b SensMiller r/w r/w r/w Description of MifNFCReg bits Symbol Description SensMiller These bits define the sensitivity of the Miller decoder ...
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... NXP Semiconductors 9.2.2.14 ManualRCVReg Allows manual fine tuning of the internal receiver. Remark: For standard applications it is not recommended to change this register settings. Table 72. Access Rights Table 73. Bit PN512 Product data sheet COMPANY PUBLIC ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b ...
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... NXP Semiconductors 9.2.2.15 TypeBReg Table 74. Access Rights Table 75. Bit 9.2.2.16 SerialSpeedReg Selects the speed of the serial UART interface. Table 76. Access Rights PN512 Product data sheet COMPANY PUBLIC TypeBReg register (address 1Eh); reset value: 00h, 00000000b RxSOF RxEOF 0 EOFSO Req Req r/w ...
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... NXP Semiconductors Table 77. Bit PN512 Product data sheet COMPANY PUBLIC Description of SerialSpeedReg bits Symbol Description BR_T0 Factor BR_T0 to adjust the transfer speed, for description see 10.3.2 “Selectable UART transfer BR_T1 Factor BR_T1 to adjust the transfer speed, for description see 10.3.2 “Selectable UART transfer All information provided in this document is subject to legal disclaimers. Rev. 3.6 — ...
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... NXP Semiconductors 9.2.3 Page 2: Configuration 9.2.3.1 PageReg Selects the register page. Table 78. Access Rights Table 79. Bit 9.2.3.2 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation. Note: The CRC is split into two 8-bit register. Note: Setting the bit MSBFirst in ModeReg register reverses the bit order, the byte order is not changed ...
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... NXP Semiconductors 9.2.3.3 GsNOffReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched off. Table 84. Access Rights Table 85. Bit PN512 Product data sheet COMPANY PUBLIC GsNOffReg register (address 23h); reset value: 88h, 10001000b ...
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... NXP Semiconductors 9.2.3.4 ModWidthReg Controls the modulation width settings. Table 86. Access Rights Table 87. Bit 9.2.3.5 TxBitPhaseReg Adjust the bitphase at 106 kbit during transmission. Table 88. Access Rights Table 89. Bit PN512 Product data sheet COMPANY PUBLIC ModWidthReg register (address 24h); reset value: 26h, 00100110b ...
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... NXP Semiconductors 9.2.3.6 RFCfgReg Configures the receiver gain and RF level detector sensitivity. Table 90. Access Rights Table 91. Bit PN512 Product data sheet COMPANY PUBLIC RFCfgReg register (address 26h); reset value: 48h, 01001000b RFLevelAmp RxGain r/w r/w r/w Description of RFCfgReg bits Symbol Description RFLevelAmp Set to logic 1, this bit activates the RF level detectors’ ...
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... NXP Semiconductors 9.2.3.7 GsNOnReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on. Table 92. Access Rights Table 93. Bit 9.2.3.8 CWGsPReg Defines the conductance of the P-driver during times of no modulation Table 94. Access Rights Table 95. ...
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... NXP Semiconductors 9.2.3.9 ModGsPReg Defines the driver P-output conductance during modulation. Table 96. Access Rights Table 97. Bit [1] If Force100ASK is set to logic 1, the value of ModGsP has no effect. 9.2.3.10 TMode Register, TPrescaler Register Defines settings for the timer. Note: The Prescaler value is split into two 8-bit registers Table 98 ...
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... NXP Semiconductors Table 99. Bit Table 100. TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b Access Rights Table 101. Description of TPrescalerReg bits Bit PN512 Product data sheet COMPANY PUBLIC Description of TModeReg bits Symbol Description TGated The internal timer is running in gated mode. Note: In the gated mode, the bit TRunning is 1 when the timer is enabled by the register bits ...
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... NXP Semiconductors 9.2.3.11 TReloadReg Describes the 16-bit long timer reload value. Note: The Reload value is split into two 8-bit registers. Table 102. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b Access Rights Table 103. Description of the higher TReloadReg bits ...
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... NXP Semiconductors 9.2.3.12 TCounterValReg Contains the current value of the timer. Note: The Counter value is split into two 8-bit register. Table 106. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh, Access Rights Table 107. Description of the higher TCounterValReg bits Bit Table 108. TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh, ...
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... NXP Semiconductors Table 111. Description of PageReg bits Bit PN512 Product data sheet COMPANY PUBLIC Symbol Description UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. ...
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... NXP Semiconductors 9.2.4.2 TestSel1Reg General test signal configuration. Table 112. TestSel1Reg register (address 31h); reset value: 00h, 00000000b Access Rights Table 113. Description of TestSel1Reg bits Bit 9.2.4.3 TestSel2Reg General test signal configuration and PRBS control Table 114. TestSel2Reg register (address 32h); reset value: 00h, 00000000b ...
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... NXP Semiconductors 9.2.4.4 TestPinEnReg Enables the pin output driver on the 8-bit parallel bus. Table 116. TestPinEnReg register (address 33h); reset value: 80h, 10000000b Access Rights Table 117. Description of TestPinEnReg bits Bit 9.2.4.5 TestPinValueReg Defines the values for the 7-bit parallel port when it is used as I/O. ...
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... NXP Semiconductors 9.2.4.6 TestBusReg Shows the status of the internal testbus. Table 120. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb Access Rights Table 121. Description of TestBusReg bits Bit 9.2.4.7 AutoTestReg Controls the digital selftest. Table 122. AutoTestReg register (address 36h); reset value: 40h, 01000000b Access Rights Table 123 ...
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... NXP Semiconductors Table 124. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb Access Rights Table 125. Description of VersionReg bits Bit PN512 Product data sheet COMPANY PUBLIC Symbol Description Version 80h indicates PN512 Version V1.0. 82h indicates PN512 Version V1.2. All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 9.2.4.9 AnalogTestReg Controls the pins AUX1 and AUX2 Table 126. AnalogTestReg register (address 38h); reset value: 00h, 00000000b 7 Access Rights r/w Table 127. Description of AnalogTestReg bits Bit Symbol Description AnalogSelAux1 Controls the AUX pin AnalogSelAux2 Note: All test signals are described in ...
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... NXP Semiconductors 9.2.4.10 TestDAC1Reg Defines the testvalues for TestDAC1. Table 128. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb Access Rights Table 129. Description of TestDAC1Reg bits Bit 9.2.4.11 TestDAC2Reg Defines the testvalue for TestDAC2. Table 130. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb ...
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... NXP Semiconductors 9.2.4.13 RFTReg Table 134. RFTReg register (address 3Ch); reset value: FFh, 11111111b Access Rights Table 135. Description of RFTReg bits Bit Table 136. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b Access Rights Table 137. Description of RFTReg bits Bit Table 138. RFTReg register (address 3Eh) ...
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... NXP Semiconductors Table 140. Connection protocol for detecting different interface types Pin SDA Table 141. Connection scheme for detecting the different interface types PN512 Pin ALE [1] A5 [1] A4 [ [2] NRD [2] NWR [2] NCS Remark: Overview on the pin behavior Pin behavior [1] only available in HVQFN 40. ...
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... NXP Semiconductors 10.2 Serial Peripheral Interface A serial peripheral interface (SPI compatible) is supported to enable high-speed communication to the host. The interface can handle data speeds Mbit/s. When communicating with a host, the PN512 acts as a slave, receiving data from the external host for register settings, sending and receiving data relevant for RF interface communication ...
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... NXP Semiconductors The first send byte defines both the mode and the address byte. Table 143. MOSI and MISO byte order Line MOSI MISO [ not care. Remark: The MSB must be sent first. 10.2.3 SPI address byte The address byte has to meet the following format. ...
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... NXP Semiconductors Table 145. BR_T0 and BR_T1 settings BR_Tn BR_T0 factor BR_T1 range Table 146. Selectable UART transfer speeds Transfer speed (kBd) 7.2 9.6 14.4 19.2 38.4 57.6 115.2 128 230.4 460.8 921.6 1228.8 [1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds. ...
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... NXP Semiconductors Remark: The LSB for data and address bytes must be sent first. No parity bit is used during transmission. Read data: To read data using the UART interface, the flow shown in used. The first byte sent defines both the mode and the address. ...
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ADDRESS ( DTRQ (1) Reserved. Fig 15. UART write data timing diagram Remark: The data byte can be sent directly after the address byte on pin RX. Address byte: The ...
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... An I C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus interface to the host. The I NXP Semiconductors’ I interface can only act in Slave mode. Therefore the PN512 does not implement clock generation or access arbitration. Fig 16. I The PN512 can act either as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode ...
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... NXP Semiconductors 10.4.1 Data validity Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW state of the data line must only change when the clock signal on SCL is LOW. Fig 17. Bit transfer on the I 10.4.2 START and STOP conditions To manage the data transfer on the I are defined ...
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... NXP Semiconductors 10.4.4 Acknowledge An acknowledge must be sent at the end of one data byte. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse ...
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... EA. If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by NXP Semiconductors and set to 0101b for all PN512 devices. The remaining 3 bits (ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer to prevent collisions with other I ...
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... NXP Semiconductors 10.4.7 Register read access To read out data from a specific register address in the PN512, the host controller must use the following procedure: • Firstly, a write access to the specific register address must be performed as indicated in the frame that follows • The first byte of a frame indicates the device address according to the I • ...
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... NXP Semiconductors 10.4.8 High-speed mode In High-speed mode (HS mode), the device can transfer information at data rates 3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode (F/S mode) for bidirectional communication in a mixed-speed bus system. 10.4.9 High-speed transfer To achieve data rates 3.4 Mbit/s the following improvements have been made to ...
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... NXP Semiconductors S SDA high SCL high Sr SDA high SCL high Master current source pull-up = Resistor pull-up 2 Fig 24. I C-bus HS mode protocol frame PN512 Product data sheet COMPANY PUBLIC 8-bit master code 0000 1xxx F/S mode R/W A 7-bit SLA mode All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 10.4.11 Switching between F/S mode and HS mode After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as Fast mode is downward-compatible with Standard mode). The connected PN512 recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting ...
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... NXP Semiconductors 11.2 Separated Read/Write strobe non multiplexed address low low low high high high multiplexed address/data AD0...AD7) address latch enable (ALE) not read strobe (NRD) not write (NWR) remark: *depending on the package type. Fig 25. Connection to host controller with separated Read/Write strobes For timing requirements refer to 11 ...
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... NXP Semiconductors 12. Analog interface and contactless UART 12.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kBd. An external circuit can be connected to the communication interface pins MFIN and MFOUT to modulate and demodulate the data ...
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... NXP Semiconductors Table 153. Register and bit settings controlling the signal on pin TX2 Bit Bit Bit Bit Tx1RFEn Force Tx2CW InvTx2RFOn 100ASK [ not care. The following abbreviations have been used in • RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2 • ...
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... NXP Semiconductors The sensitivity of the RF level detector is adjustable in a 4-bit range using the bits RFLevel in register RFCfgReg. The sensitivity itself depends on the antenna configuration and tuning. Possible sensitivity levels at the RX pin are listed in the Table 154. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated) ...
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... NXP Semiconductors Fig 27. Data mode detector PN512 Product data sheet COMPANY PUBLIC HOST INTERFACES REGISTERS REGISTERSETTING FOR THE DETECTED MODE NFC @ 106 kbit/s NFC @ 212 kbit/s NFC @ 424 kbit/s DATA MODE DETECTOR RECEIVER I/Q DEMODULATOR PN512 RX All information provided in this document is subject to legal disclaimers. ...
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... ISO/IEC 14443A signal sent by the secure IC. The SIGOUT pin can provide a digital signal and a clock to communicate to the secure IC. A secure IC can be the smart card IC provided by NXP Semiconductors. The PN512 has an extra supply pin (SVDD and PVSS as Ground line) for the SIGIN and SIGOUT pads ...
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... NXP Semiconductors Fig 29. Communication flows using the S Configured in the Secure Access Mode the host controller can directly communicate to the Secure IC via SIGIN/SIGOUT. In this mode the PN512 generates the RF clock and performs the communication on the SIGOUT line. To enable the Secure Access module mode the clock has to be derived by the internal oscillator of the PN512, see bits SAMClockSel in register TestSel1Reg ...
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... NXP Semiconductors 12.6.1 Signal shape for Felica S The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN. The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized demodulated signal. The clock and the demodulated signal is combined by using the logical function exclusive or ...
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... NXP Semiconductors 12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S The secure IC, e.g. the SmartMX is connected to the PN512 via the pins SIGOUT and SIGIN. The waveform shape at SIGOUT is a digital 13.56 MHz Miller coded signal with levels between PVSS and PVDD derived out of the external 13.56 MHz carrier signal in case of the Contactless Card mode or internally generated in terms of Secure Access mode ...
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... NXP Semiconductors 12.7 Hardware support for FeliCa and NFC polling 12.7.1 Polling sequence functionality for initiator 1. Timer: The PN512 has a timer, which can be programmed in a way that it generates an interrupt at the end of each timeslot required an interrupt is generated at the end of the last timeslot. ...
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... NXP Semiconductors 12.7.3 Additional hardware support for FeliCa and NFC Additionally to the polling sequence support for the Felica mode, the PN512 supports the check of the Len-byte. The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg: DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet length ...
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... NXP Semiconductors 13. FIFO buffer An 8 × 64 bit FIFO buffer is used in the PN512. It buffers the input and output data stream between the host and the PN512’s internal state machine. This makes it possible to manage data streams bytes long without the need to take timing constraints into account ...
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... NXP Semiconductors If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the LoAlert bit is set to logic generated according to Equation LoAlert 14. Interrupt request system The PN512 indicates certain events by setting the Status1Reg register’s IRq bit and, if activated, by pin IRQ ...
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... NXP Semiconductors 15. Timer unit A timer unit is implemented in the PN512. The external host controller may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations: • Time-out counter • Watch-dog counter • Stop watch • Programmable one-shot • ...
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... NXP Semiconductors To indicate required to count 339 clock cycles. This means the value for TPrescaler has to be set to TPrescaler = 169.The timer has now an input clock of 25 us. The timer can count up to 65535 timeslots of each 25 μs. PN512 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 16. Power reduction modes 16.1 Hard power-down Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pins and clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or LOW level ...
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... NXP Semiconductors 17. Oscillator circuitry Fig 34. Quartz crystal connection The clock applied to the PN512 provides a time basis for the synchronous system’s encoder and decoder. The stability of the clock frequency, therefore important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible ...
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... NXP Semiconductors device activation Fig 35. Oscillator start-up time 19. PN512 command set The PN512 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer ...
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... NXP Semiconductors 19.3 PN512 command overview Table 157. Command overview Command Idle Mem Generate RandomID CalcCRC Transmit NoCmdChange Receive Transceive - MFAuthent SoftReset 19.3.1 PN512 command descriptions 19.3.1.1 Idle Places the PN512 in Idle mode. The Idle command also terminates itself. 19.3.1.2 Mem Transfers 25 bytes from the FIFO buffer to the internal buffer ...
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... NXP Semiconductors The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The value is loaded in to the CRC coprocessor when the command starts. This command must be terminated by writing a command to the CommandReg register, such as, the Idle command. If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the PN512 enters Self Test mode ...
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... NXP Semiconductors • Authentication command code (60h, 61h) • Block address • Sector key byte 0 • Sector key byte 1 • Sector key byte 2 • Sector key byte 3 • Sector key byte 4 • Sector key byte 5 • Card serial number byte 0 • ...
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... NXP Semiconductors 20. Testsignals 20.1 Selftest The PN512 has the capability to perform a digital selftest. To start the selftest the following procedure has to be performed: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command. 3. Enable the Selftest by writing the value 09h to the register AutoTestReg. ...
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... NXP Semiconductors Table 161. Description of Testsignals Pins Table 162. Testsignal routing (TestSel2Reg = 19h) Pins Testsignal Table 163. Description of Testsignals Pins 20.3 Testsignals at pin AUX Table 164. Testsignals description SelAux 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 ...
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... NXP Semiconductors Note: The DAC has a current output recommended to use a 1 kΩ pull-down resistance at pins AUX1/AUX2. 20.4 PRBS Enables the PRBS9 or PRBS15 sequence according to ITU-TO150. To start the transmission of the defined datastream the command send has to be activated. The preamble/Sync byte/start bit/parity bit are generated automatically depending on the selected mode ...
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... NXP Semiconductors 22. Limiting values Table 165. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V analog supply voltage DDA V digital supply voltage DDD V PVDD supply voltage DD(PVDD) V TVDD supply voltage DD(TVDD) V SVDD supply voltage DD(SVDD) V input voltage ...
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... NXP Semiconductors 24. Thermal characteristics Table 167. Thermal characteristics Symbol Parameter R Thermal resistance from thj-a junction to ambient 25. Characteristics Table 168. Characteristics Symbol Parameter Input characteristics 2 Pins EA and NRSTPD I input leakage current LI V HIGH-level input voltage IH V LOW-level input voltage IL Pin SIGIN I input leakage current ...
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... NXP Semiconductors Table 168. Characteristics …continued Symbol Parameter C input capacitance i Input/output characteristics pins D1, D2, D3, D4, D5, D6 and D7 I input leakage current LI V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I HIGH-level output current ...
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... NXP Semiconductors Table 168. Characteristics …continued Symbol Parameter Pins TX1 and TX2 V HIGH-level output voltage OH V LOW-level output voltage OL Current consumption I power-down current pd I digital supply current DDD I analog supply current DDA I PVDD supply current DD(PVDD) I TVDD supply current DD(TVDD) I SVDD supply current ...
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... NXP Semiconductors Table 168. Characteristics …continued Symbol Parameter V LOW-level output voltage OL C input capacitance i Typical input requirements f crystal frequency xtal ESR equivalent series resistance C load capacitance L P crystal power dissipation xtal [1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD. ...
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... NXP Semiconductors Table 169. SPI timing characteristics Symbol t su(D-SCKH) t h(SCKL-Q) t (SCKL-NSSH) Table 170. I Symbol Parameter f SCL t HD;STA t SU;STA t SU;STO t LOW t HIGH t HD;DAT t SU;DAT BUF PN512 Product data sheet COMPANY PUBLIC …continued Parameter Conditions data input to SCK HIGH changing MOSI to set-up time ...
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... NXP Semiconductors SCK MOSI MISO NSS Fig 38. Timing diagram for SPI SDA SCL Fig 39. Timing for Fast and Standard mode devices on the I PN512 Product data sheet COMPANY PUBLIC t t SCKL SCKH t t DXSH SHDX MSB MSB Remark: The signal NSS must be LOW to be able to send several bytes in one data stream. ...
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... NXP Semiconductors 25.2 8-bit parallel interface timing 25.2.1 AC symbols Each timing symbol has five characters. The first character is always 't' for time. The other characters indicate the name of a signal or the logic state of that signal (depending on position): Table 171. AC symbols Designation Example ...
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... NXP Semiconductors ALE NCS NWR NRD D0...D7 A0...A3 Fig 40. Timing diagram for separated Read/Write strobe Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines have to be connected as described in chapter Automatic host controller Interface Type Detection ...
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... NXP Semiconductors ALE NCS R/NW NDS D0...D7 A0...A3 Fig 41. Timing diagram for common Read/Write strobe Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines have to be connected as described in Automatic μ ...
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... NXP Semiconductors 26. Package information The PN512 can be delivered in 2 different packages. Table 174. Package information Package HVQFN32 HVQFN40 PN512 Product data sheet COMPANY PUBLIC Remarks 8-bit parallel interface not supported Supports the 8-bit parallel interface All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 27. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 0.85 mm terminal 1 index area terminal 1 40 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 28. Abbreviations Table 175. Abbreviations Acronym ADC ASK BPSK CRC CW DAC EOF HBM LSB MISO MM MOSI MSB NSS PCB PLL PRBS RX SOF SPI TX UART 29. Glossary Modulation index — Defined as the voltage ratio (V Load modulation index — Defined as the voltage ratio for the card − ...
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... NXP Semiconductors 31. Revision history Table 176. Revision history Document ID Release date PN512 v.3.6 20110310 • Modifications: Figure 36 “Typical circuit diagram” on page PN512 v.3.5 20110211 • Table 2 Modifications: • General re-wording of MIFARE designation and commercial conditions. • Graphics: updated to latest standard. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 34. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .4 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .4 Table 3. Pin description HVQFN32 . . . . . . . . . . . . . . . . .8 Table 4. Pin description HVQFN40 . . . . . . . . . . . . . . . . .9 Table 5. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer . . . . .10 Table 6. Communication overview for FeliCa reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 7. FeliCa framing and coding . . . . . . . . . . . . . . . .12 Table 8. Start value for the CRC Polynomial: (00h), (00h)12 Table 9 ...
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... NXP Semiconductors Table 78. PageReg register (address 20h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 79. Description of PageReg bits . . . . . . . . . . . . . . .48 Table 80. CRCResultReg register (address 21h); reset value: FFh, 11111111b .48 Table 81. Description of CRCResultReg bits . . . . . . . . . .48 Table 82. CRCResultReg register (address 22h); reset value: FFh, 11111111b .48 Table 83. Description of CRCResultReg bits . . . . . . . . . .48 Table 84. GsNOffReg register (address 23h) ...
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... NXP Semiconductors Table 158. Testsignal routing (TestSel2Reg = 07h .101 Table 159. Description of Testsignals . . . . . . . . . . . . . . .101 Table 160. Testsignal routing (TestSel2Reg = 0Dh .101 Table 161. Description of Testsignals . . . . . . . . . . . . . . .102 Table 162. Testsignal routing (TestSel2Reg = 19h .102 Table 163. Description of Testsignals . . . . . . . . . . . . . . .102 Table 164. Testsignals description .102 Table 165 ...
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... NXP Semiconductors 35. Figures Fig 1. Simplified block diagram of the PN512 . . . . . . . . .5 Fig 2. Detailed block diagram of the PN512 . . . . . . . . . .6 Fig 3. Pinning configuration HVQFN32 (SOT617- Fig 4. Pinning configuration HVQFN40 (SOT618- Fig 5. PN512 Read/Write mode . . . . . . . . . . . . . . . . . . .10 Fig 6. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram .10 Fig 7. Data coding and framing according to ISO/IEC 14443 A ...
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... NXP Semiconductors 36. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 3 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 4 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 Functional description . . . . . . . . . . . . . . . . . . 10 8.1 ISO/IEC 14443 A/MIFARE functionality . . . . . 10 8.2 ISO/IEC 14443 B functionality . . . . . . . . . . . . 11 8 ...
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... NXP Semiconductors 11.1 Overview of supported host controller interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.2 Separated Read/Write strobe . . . . . . . . . . . . . 80 11.3 Common Read/Write strobe . . . . . . . . . . . . . . 80 12 Analog interface and contactless UART . . . . 81 12.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.2 TX driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.3 RF level detector . . . . . . . . . . . . . . . . . . . . . . 82 12.4 Data mode detector . . . . . . . . . . . . . . . . . . . . 83 12.5 Serial data switch . . . . . . . . . . . . . . . . . . . . . . interface support . . . . . . . . . . . . . . . . . . . 85 12.6.1 Signal shape for Felica S 12 ...