PN5120A0HN/C2,551 NXP Semiconductors, PN5120A0HN/C2,551 Datasheet - Page 44

• Manufacturer Part Number: PN5120A0HN/C2,551
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C2,551

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.2.13 MifNFCReg
Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating
mode.
Table 70.
Table 71.
Bit
7 to 5
4 to 3
2
1 to 0
Access
Rights
Symbol
SensMiller
TauMiller
MFHalted
TxWait
MifNFCReg register (address 1Ch); reset value: 62h, 01100010b
Description of MifNFCReg bits
r/w
7
All information provided in this document is subject to legal disclaimers.
SensMiller
Rev. 3.6 — 10 March 2011
r/w
6
Description
These bits define the sensitivity of the Miller decoder.
These bits define the time constant of the Miller decoder.
Set to logic 1, this bit indicates that the PN512 is set to HALT mode in
Card Operation mode at 106 kbit. This bit is either set by the host
controller or by the internal state machine and indicates that only the
code 52h is accepted as a request command. This bit is cleared
automatically by a RF reset.
These bits define the additional response time for the target at 106 kbit
in Passive Communication mode and during the AutoColl command.
Per default 7 bits are added to the value of the register bit.
111336
r/w
5
r/w
4
TauMiller
r/w
3
MFHalted
r/w
2
Transmission module
© NXP B.V. 2011. All rights reserved.
r/w
1
PN512
TxWait
44 of 125
r/w
0