PCF8562TT/2,518 NXP Semiconductors, PCF8562TT/2,518 Datasheet - Page 14

• Manufacturer Part Number: PCF8562TT/2,518
• Description: LCD Drivers LCD DRIVER 32/128SEG
• Manufacturer: NXP Semiconductors

Specifications of PCF8562TT/2,518

• Number Of Digits: 16
• Number Of Segments: 128
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-48
• Maximum Supply Current: 20 uA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935276218518 PCF8562TT/2-T

NXP Semiconductors
PCF8562_5
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing
7.7 Display register
7.8 Segment outputs
7.9 Backplane outputs
The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal
oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC
to pin V
Pin CLK is enabled as an external clock input by connecting pin OSC to V
The LCD frame signal frequency is determined by the clock frequency (f
A clock signal must always be supplied to the device; removing the clock freezes the LCD
in a DC state.
The PCF8562 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division of the clock frequency from either
the internal or an external clock:
The display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs and each column of the display RAM.
The LCD drive section includes 32 segment outputs S0 to S31 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display latch. When
less than 32 segment outputs are required, the unused segment outputs should be left
open-circuit.
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals
and may also be paired to increase the drive capabilities.
In the static drive mode the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
SS
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All information provided in this document is subject to legal disclaimers.
Rev. 05 — 19 May 2010
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Universal LCD driver for low multiplex rates
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PCF8562
© NXP B.V. 2010. All rights reserved.
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