AD7606BSTZ-6RL Analog Devices Inc, AD7606BSTZ-6RL Datasheet - Page 26

• Manufacturer Part Number: AD7606BSTZ-6RL
• Description: Simulat Sampliing Bipolar 16 Bit I.C.
• Manufacturer: Analog Devices Inc
• Type: Data Acquisition System (DAS), ADCr

Specifications of AD7606BSTZ-6RL

• Design Resources: Layout Considerations for an Expandable Multichannel Simultaneous Sampling Data Acquisition System Based on AD7606 (CN0148)
• Resolution (bits): 16 b
• Sampling Rate (per Second): 200k
• Data Interface: DSP, MICROWIRE™, Parallel, QSPI™, Serial, SPI™
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD7606BSTZ-6RL

AD7606/AD7606-6/AD7606-4
CONVERSION CONTROL
Simultaneous Sampling on All Analog Input Channels
The AD7606/AD7606-6/AD7606-4 allow simultaneous sampling
of all analog input channels. All channels are sampled simul-
taneously when both CONVST pins (CONVST A, CONVST B)
are tied together. A single CONVST signal is used to control both
CONVST x inputs. The rising edge of this common CONVST
signal initiates simultaneous sampling on all analog input channels
(V1 to V8 for the AD7606, V1 to V6 for the AD7606-6, and V1
to V4 for the AD7606-4).
The AD7606 contains an on-chip oscillator that is used to
perform the conversions. The conversion time for all ADC
channels is t
conversions are in progress, so when the rising edge of CONVST
is applied, BUSY goes logic high and transitions low at the end
of the entire conversion process. The falling edge of the BUSY
signal is used to place all eight track-and-hold amplifiers back
into track mode. The falling edge of BUSY also indicates that
the new data can now be read from the parallel bus (DB[15:0]),
the D
DB[7:0].
Simultaneously Sampling Two Sets of Channels
The AD7606/AD7606-6/AD7606-4 also allow the analog input
channels to be sampled simultaneously in two sets. This can be
used in power-line protection and measurement systems to
compensate for phase differences introduced by PT and CT
OUT
A and D
CONV
Figure 44. AD7606 Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Mode
. The BUSY signal indicates to the user when
OUT
DATA: DB[15:0]
B serial data lines, or the parallel byte bus,
FRSTDATA
CONVST A
CONVST B
CS/RD
BUSY
V1 TO V4 TRACK-AND-HOLD
ENTER HOLD
t
5
t
CONV
ON ALL 8 CHANNELS
V5 TO V8 TRACK-AND-HOLD
ENTER HOLD
AD7606 CONVERTS
Rev. A | Page 26 of 36
V1
V2
transformers. In a 50 Hz system, this allows for up to 9° of phase
compensation; and in a 60 Hz system, it allows for up to 10° of
phase compensation.
This is accomplished by pulsing the two CONVST pins
independently and is possible only if oversampling is not in use.
CONVST A is used to initiate simultaneous sampling of the
first set of channels (V1 to V4 for the AD7606, V1 to V3 for the
AD7606-6, and V1 and V2 for the AD7606-4); and CONVST B
is used to initiate simultaneous sampling on the second set of
analog input channels (V5 to V8 for the AD7606, V4 to V6 for
the AD7606-6, and V3 and V4 for the AD7606-4), as illustrated
in Figure 44. On the rising edge of CONVST A, the track-and-
hold amplifiers for the first set of channels are placed into hold
mode. On the rising edge of CONVST B, the track-and-hold
amplifiers for the second set of channels are placed into hold
mode. The conversion process begins once both rising edges
of CONVST x have occurred; therefore BUSY goes high on the
rising edge of the later CONVST x signal. In Table 3, Time t
indicates the maximum allowable time between CONVST x
sampling points.
There is no change to the data read process when using two
separate CONVST x signals.
Connect all unused analog input channels to AGND. The results
for any unused channels are still included in the data read because
all channels are always converted.
V3
V7
V8
5