AD7606BSTZ-6RL Analog Devices Inc, AD7606BSTZ-6RL Datasheet - Page 27

• Manufacturer Part Number: AD7606BSTZ-6RL
• Description: Simulat Sampliing Bipolar 16 Bit I.C.
• Manufacturer: Analog Devices Inc
• Type: Data Acquisition System (DAS), ADCr

Specifications of AD7606BSTZ-6RL

• Design Resources: Layout Considerations for an Expandable Multichannel Simultaneous Sampling Data Acquisition System Based on AD7606 (CN0148)
• Resolution (bits): 16 b
• Sampling Rate (per Second): 200k
• Data Interface: DSP, MICROWIRE™, Parallel, QSPI™, Serial, SPI™
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD7606BSTZ-6RL

DIGITAL INTERFACE
The AD7606/AD7606-6/AD7606-4 provide three interface
options: a parallel interface, a high speed serial interface, and
a parallel byte interface. The required interface mode is selected
via the PAR /SER/BYTE SEL and DB15/BYTE SEL pins.
Table 8. Interface Mode Selection
PAR/SER/BYTE SEL
0
1
1
Operation of the interface modes is discussed in the following
sections.
PARALLEL INTERFACE (PAR/SER/BYTE SEL = 0)
Data can be read from the AD7606/AD7606-6/AD7606-4 via
the parallel data bus with standard CS and RD signals. To read the
data over the parallel bus, the PAR /SER/BYTE SEL pin should
be tied low. The CS and RD input signals are internally gated to
enable the conversion result onto the data bus. The data lines,
DB15 to DB0, leave their high impedance state when both CS
and RD are logic low.
The rising edge of the CS input signal three-states the bus, and
the falling edge of the CS input signal takes the bus out of the
high impedance state. CS is the control signal that enables the
data lines; it is the function that allows multiple AD7606/
AD7606-6/ AD7606-4 devices to share the same parallel
data bus.
The CS signal can be permanently tied low, and the RD signal
can be used to access the conversion results as shown in
A read operation of new data can take place after the BUSY
signal goes low (see
of data from the previous conversion process can take place
while BUSY is high (see
The RD pin is used to read data from the output conversion
results register. Applying a sequence of RD pulses to the RD pin
of the AD7606/AD7606-6/AD7606-4 clocks the conversion
results out from each channel onto the Parallel Bus DB[15:0] in
ascending order. The first RD falling edge after BUSY goes low
clocks out the conversion result from Channel V1. The next RD
falling edge updates the bus with the V2 conversion result, and so
on. On the AD7606, the eighth falling edge of RD clocks out the
conversion result for Channel V8.
Figure 45. AD7606 Interface Diagram—One AD7606 Using the Parallel Bus,
AD7606
with CS and RD Shorted Together
RD/SCLK
DB[15:0]
Figure 2
BUSY
DB15
0
0
1
CS
Figure 3
14
13
12
[33:24]
[22:16]
); or, alternatively, a read operation
INTERRUPT
).
Interface Mode
Parallel interface mode
Serial interface mode
Parallel byte interface mode
DIGITAL
HOST
Figure 4
Rev. A | Page 27 of 36
.
When the RD signal is logic low, it enables the data conversion
result from each channel to be transferred to the digital host
(DSP, FPGA).
When there is only one AD7606/AD7606-6/AD7606-4 in
a system/board and it does not share the parallel bus, data can
be read using just one control signal from the digital host. The
CS and RD signals can be tied together, as shown in
In this case, the data bus comes out of three-state on the falling
edge of
to be clocked out of the AD7606/AD7606-6/AD7606-4 and to
be read by the digital host. In this case, CS is used to frame the
data transfer of each data channel.
PARALLEL BYTE (PAR/SER/BYTE SEL = 1, DB15 = 1)
Parallel byte interface mode operates much like the parallel
interface mode, except that each channel conversion result is read
out in two 8-bit transfers. Therefore, 16 RD pulses are required
to read all eight conversion results from the AD7606. For the
AD7606-6, 12 RD pulses are required; and on the AD7606-4,
eight RD pulses are required to read all the channel results.
To configure the AD7606/AD76706-6/AD7606-4 to operate in
parallel byte mode, the PAR /SER/BYTE SEL and BYTE SEL/
DB15 pins should be tied to logic high (see
byte mode, DB[7:0] are used to transfer the data to the digital
host. DB0 is the LSB of the data transfer, and DB7 is the MSB of
the data transfer. In parallel byte mode, DB14 acts as an HBEN
pin. When DB14/HBEN is tied to logic high, the most
significant byte (MSB) of the conversion result is output first,
followed by the LSB of the conversion result. When DB14 is tied
to logic low, the LSB of the conversion result is output first,
followed by the MSB of the conversion result. The FRSTDATA
pin remains high until the entire 16 bits of the conversion result
from V1 are read from the AD7606/AD7606-6/AD7606-4.
SERIAL INTERFACE (PAR/SER/BYTE SEL = 1)
To read data back from the AD7606 over the serial interface, the
PAR /SER/BYTE SEL pin must be tied high. The CS and SCLK
signals are used to transfer data from the AD7606. The AD7606/
AD7606-6/AD7606-4 have two serial data output pins, D
and D
6/AD7606-4 using one or both of these D
AD7606, conversion results from Channel V1 to Channel V4
first appear on D
to Channel V8 first appear on D
conversion results from Channel V1 to Channel V3 first appear
on D
V6 first appear on D
from Channel V1 and Channel V2 first appear on D
conversion results from Channels V3 and Channel V4 first
appear on D
OUT
OUT
CS / RD . The combined CS and RD signal allows the data
A, and conversion results from Channel V4 to Channel
B. Data can be read back from the AD7606/AD76706-
OUT
B.
OUT
AD7606/AD7606-6/AD7606-4
A, and conversion results from Channel V5
OUT
B. For the AD7606-4, conversion results
OUT
B. For the AD7606-6,
OUT
Table 8
lines. For the
). In parallel
OUT
Figure 5
A, and
OUT
A
.