AD9627-125EBZ Analog Devices Inc, AD9627-125EBZ Datasheet - Page 13

• Manufacturer Part Number: AD9627-125EBZ
• Description: 12Bit 125 Msps Dual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9627-125EBZ

• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 125M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 900mW @ 125MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9627
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Table 8.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
SPORT TIMING REQUIREMENTS
Timing Diagrams
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CSSCLK
SSCLKSDO
SSCLKSDFS
CH A/CH B DATA
CH A/CH B FAST
DCOA/DCOB
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
DETECT
CLK+
CLK–
Conditions
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
Delay from rising edge of CLK+ to rising edge of SMI SCLK
Delay from rising edge of SMI SCLK to SMI SDO
Delay from rising edge of SMI SCLK to SMI SDFS
N – 13
N – 3
N
t
S
t
t
A
PD
N – 12
N – 2
N + 1
t
CLK
t
H
N – 11
N + 2
N – 1
Rev. B | Page 13 of 76
N – 10
N + 3
N
t
DCO
N – 9
N + 1
N + 4
N – 8
N + 2
N + 5
t
CLK
N + 6
N + 3
N – 7
N + 7
N – 6
N + 4
Min
2
2
40
2
2
10
10
10
10
3.2
−0.4
−0.4
N + 8
N – 5
N + 5
N – 4
N + 6
Typ
0.24
0.40
4.5
0
0
Max
6.2
0.4
0.4
AD9627
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns