AD9627-125EBZ Analog Devices Inc, AD9627-125EBZ Datasheet - Page 18

• Manufacturer Part Number: AD9627-125EBZ
• Description: 12Bit 125 Msps Dual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9627-125EBZ

• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 125M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 900mW @ 125MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9627
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9627
Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
ADC Power Supplies
20, 64
1, 21
24, 57
36, 45, 46
0
2, 3, 62,
63
ADC Analog
37
38
44
43
39
40
42
41
49
50
ADC Fast Detect Outputs
54
53
56
55
59
58
61
60
Digital Input
52
Mnemonic
DRGND
DRVDD
DVDD
AVDD
AGND
DNC
VIN+A
VIN−A
VIN+B
VIN−B
VREF
SENSE
RBIAS
CML
CLK+
CLK−
FD0+
FD0−
FD1+
FD1−
FD2+
FD2−
FD3+
FD3−
SYNC
Type
Ground
Supply
Supply
Supply
Ground
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Input
D0– (LSB)
D0+ (LSB)
DRVDD
DCO–
DCO+
Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
DNC
DNC
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
D1–
D1+
D2–
D2+
D3–
D3+
D4–
D4+
D5–
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Description
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
Do Not Connect.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 14 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 17 for details.
Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 17 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 17 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 17 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 17 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 17 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 17 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 17 for details.
Digital Synchronization Pin. Slave mode only.
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
PARALLEL LVDS
Rev. B | Page 18 of 76
(Not to Scale)
AD9627
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB