AD9627-125EBZ Analog Devices Inc, AD9627-125EBZ Datasheet - Page 16

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AD9627-125EBZ

Manufacturer Part Number
AD9627-125EBZ
Description
12Bit 125 Msps Dual 1.8V PB Free ADC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9627-125EBZ

Number Of Adc's
2
Number Of Bits
12
Sampling Rate (per Second)
125M
Data Interface
Serial
Inputs Per Adc
1 Differential
Input Range
2 Vpp
Power (typ) @ Conditions
900mW @ 125MSPS
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD9627
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9627
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 11. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
ADC Power Supplies
20, 64
1, 21
24, 57
36, 45, 46
0
12, 13, 58, 59
ADC Analog
37
38
44
43
39
40
42
41
49
50
ADC Fast Detect Outputs
29
30
31
32
53
54
55
56
AVDD
AGND
SENSE
CLK+
FD0A
FD1A
FD2A
FD3A
FD0B
FD1B
FD2B
FD3B
Mnemonic
DRGND
DRVDD
DVDD
DNC
VIN+A
VIN−A
VIN+B
VIN−B
VREF
RBIAS
CML
CLK−
D11B (MSB)
D0A (LSB)
Type
Ground
Supply
Supply
Supply
Ground
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
DRVDD
DCOB
DCOA
D10B
DNC
DNC
D4B
D5B
D6B
D7B
D8B
D9B
D1A
D2A
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Description
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
Do Not Connect.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 14 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Channel A Fast Detect Indicator. See Table 17 for details.
Channel A Fast Detect Indicator. See Table 17 for details.
Channel A Fast Detect Indicator. See Table 17 for details.
Channel A Fast Detect Indicator. See Table 17 for details.
Channel B Fast Detect Indicator. See Table 17 for details.
Channel B Fast Detect Indicator. See Table 17 for details.
Channel B Fast Detect Indicator. See Table 17 for details.
Channel B Fast Detect Indicator. See Table 17 for details.
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
PARALLEL CMOS
Rev. B | Page 16 of 76
(Not to Scale)
AD9627
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB

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