AD9627-125EBZ Analog Devices Inc, AD9627-125EBZ Datasheet - Page 26

• Manufacturer Part Number: AD9627-125EBZ
• Description: 12Bit 125 Msps Dual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9627-125EBZ

• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 125M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 900mW @ 125MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9627
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9627
THEORY OF OPERATION
The AD9627 dual ADC design can be used for diversity reception
of signals, where the ADCs are operating identically on the same
carrier but from two separate antennae. The ADCs can also be
operated with independent analog inputs. The user can sample
any f
low-pass or band-pass filtering at the ADC inputs with little loss
in ADC performance. Operation to 450 MHz analog input is
permitted but occurs at the expense of increased ADC noise and
distortion.
In nondiversity applications, the AD9627 can be used as a base-
band or direct downconversion receiver, where one ADC is
used for I input data, and the other is used for Q input data.
Synchronizaton capability is provided to allow synchronized
timing between multiple channels or multiple devices.
Programming and control of the AD9627 are accomplished
using a 3-bit SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9627 architecture consists of a dual front-end sample-
and-hold amplifier (SHA), followed by a pipelined, switched
capacitor ADC. The quantized outputs from each stage are
combined into a final 12-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate on
a new input sample and the remaining stages to operate on the
preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The residue amplifier magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential SHA that
can be ac- or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, corrects errors, and passes
the data to the output buffers. The output buffers are powered from
a separate supply, allowing adjustment of the output voltage swing.
During power-down, the output buffers go into a high impedance
state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9627 is a differential switched
capacitor SHA that has been designed for optimum performance
while processing a differential input signal.
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 45). When the SHA is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within 1/2 of a clock cycle.
S
/2 frequency segment from dc to 200 MHz, using appropriate
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A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, any
shunt capacitors should be reduced. In combination with the
driving source impedance, the shunt capacitors limit the input
bandwidth. Refer to Application Note AN-742, Frequency
Domain Response of Switched-Capacitor ADCs; Application Note
AN-827, A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs; and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D Converters, ”
for more information on this subject (see www.analog.com).
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by this buffer to 2 × VREF.
Input Common Mode
The analog inputs of the AD9627 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that V
is recommended for optimum performance, but the device
functions over a wider range with reasonable performance
(see Figure 44). An on-board common-mode voltage reference
is included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage
(typically 0.55 × AVDD). The CML pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Applications
Information section.
Differential Input Configurations
Optimum performance is achieved while driving the AD9627 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-2, and
excellent performance and a flexible interface to the ADC.
VIN+
VIN–
C
C
PIN, PAR
PIN, PAR
Figure 45. Switched-Capacitor SHA Input
S
S
H
ADA4938-2
C
C
S
S
CM
differential drivers provide
= 0.55 × AVDD
C
C
S
S
H
H